
95
ATmega8515(L)
2512A–AVR–04/02
Figure 46. 16-bit Timer/CounterBlock Diagram
(1)
Note: 1. Refer to Figure1onpage 2, Table29 on page 64, and Table 35onpage 69 for
Timer/Counter1 pin placement anddescription.
Registers The
Timer/Counter
(TCNT1),
Output Compare Registers
(OCR1A/B), and
Input Capture
Register
(ICR1) areall 16-bit registers. Specialprocedures must be followedwhen
accessing the16-bit registers.These procedures are described in the section “Access-
ing 16-bit Registers”onpage 97.The
Timer/Counter Control Registers
(TCCR1A/B) are
8-bit registers andhave no CPU access restrictions. Interrupt requests(abbreviated to
Int.Req.inthe figure)signals areall visibleinthe
Timer Interrupt Flag Register
(TIFR).
All interrupts areindividually maskedwith the
Timer Interrupt Mask Register
(TIMSK).
TIFRand TIMSK arenotshowninthe figure sincethese registers are sharedbyother
timer units.
TheTimer/Countercan be clocked internally, via the prescaler, orbyan externalclock
sourceontheT1pin. The Clock Select logicblock controls which clock sourceand edge
theTimer/Counter uses to increment (ordecrement) its value. TheTimer/Counter is
inactive when no clock sourceisselected.Theoutput from the clock select logic is
referred to as thetimerclock (clk
T
1
).
The double bufferedOutput CompareRegisters (OCR1A/B) are comparedwith the
Timer/Counter value at all time. The resultof the compare can beusedbythe waveform
generator to generate a PWM or variable frequency output on the Output ComparePin
(OC1A/B). See “Output Compare Units”onpage 103.The comparematch event will
Clock Select
Timer/Counter
DATA BUS
OCRnA
OCRnB
ICRn
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
=
0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
ICFn (Int.Req.)
TCCRnA TCCRnB
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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