
154
ATmega8515(L)
2512A–AVR–04/02
• Bit 3 – USBS: Stop Bit Select
Thisbit selects the number ofstopbits to beinsertedbytheTransmitter.TheReceiver
ignores thissetting.
• Bit 2:1 – UCSZ1:0: Character Size
The UCSZ1:0 bitscombinedwith the UCSZ2 bit in UCSRBsets the number ofdata bits
(charactersize) in a frame the receiver and transmitter use.
• Bit 0 – UCPOL: Clock Polarity
Thisbit is usedforSynchronous modeonly. Write thisbit to zero when Asynchronous
modeis used.The UCPOL bit sets the relationshipbetween data output change and
data input sample, and the synchronousclock (XCK).
Table 64. UPMBitsSettings
UPM1 UPM0 Parity Mode
00Disabled
01Reserved
10Enabled, Even Parity
11Enabled, Odd Parity
Table 65. USBS Bit Settings
USBS Stop Bit(s)
01-bit
12-bit
Table 66. UCSZ BitsSettings
UCSZ2 UCSZ1 UCSZ0 Character Size
0005-bit
0016-bit
0107-bit
0118-bit
100Reserved
101Reserved
110Reserved
1119-bit
Table 67. UCPOL Bit Settings
UCPOL
Transmitted Data Changed
(OutputofTxDPin)
Received Data Sampled
(Input on RxD Pin)
0 Falling XCK Edge Rising XCK Edge
1Rising XCK Edge Falling XCK Edge
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