
93
ATmega8515(L)
2512A–AVR–04/02
theedge detector usessampling, themaximum frequency of an externalclock it can
detectishalf the sampling frequency (Nyquist sampling theorem). However, due to vari-
ation of the system clock frequency andduty cycle causedbyOscillatorsource (crystal,
resonator, andcapacitors) tolerances, it isrecommended that maximum frequency of an
externalclock sourceisless than f
clk_I/O
/2.5.
An externalclock source can not be prescaled.
Figure 45. Prescalerfor Timer/Counter0and Timer/Counter1
(1)
Note: 1. The synchronization logic on theinput pins(T1/T0) isshowninFigure 44.
Special Function IO Register –
SFIOR
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When thisbit iswrittentoone, theTimer/Counter1and Timer/Counter0 prescalerwill be
reset. The bit will be clearedbyhardwareafter theoperation isperformed. Writing a
zerotothisbit will havenoeffect. Note that Timer/Counter1and Timer/Counter0 share
the same prescaler and a reset of thisprescalerwill affect both timers.Thisbit will
always be read aszero.
PSR10
Clear
clk
T1
clk
T0
T1
T0
clk
I/O
Synchronization
Synchronization
Bit 76543 210
– XMBK XMM2 XMM1 XMM0 PUD –PSR10SFIOR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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