24
ATmega8515(L)
2512A–AVR–04/02
data direction settings areused. Note that when the XMEM interfaceisdisabled, the
address spaceabove theinternalSRAMboundary is not mapped into theinternal
SRAM. Figure12illustrateshow to connectanexternalSRAM to the AVR using an octal
latch (typically “74x573”or equivalent)which is transparent when G ishigh.
Address Latch Requirements Due to the high-speed operation of the XRAM interface, theaddress latch must be
selectedwithcare for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.
When operating at conditions above these frequencies, thetypical old style 74HC series
latch becomes inadequate. Theexternal memory interfaceisdesigned in complianceto
the 74AHC serieslatch. However, most latchescan beused aslong theycomply with
themaintimingparameters.Themainparameters for theaddress latch are:
• D to Qpropagation delay(t
pd
)
• Data setup time before Glow(t
su
)
• Data (address) hold time afterGlow(
th
)
Theexternal memory interfaceisdesigned to guaranty minimum address hold time after
G is assertedlow of t
h
= 5ns(refer to t
LAXX_LD
/t
LLAXX_ST
in Table 99 to Table106 on page
201).The D to Qpropagation delay(t
pd
) must betaken into consideration when calculat-
ing theaccess time requirement of theexternalcomponent. The data setup time before
Glow(t
su
) mustnotexceed address valid to ALE low(t
AVLLC
) minus PCB wiring delay
(dependent on the capacitive load).
Figure 12. ExternalSRAMConnected to the AVR
Pull-up and Bus Keeper The pull-upresistors on theAD7:0 ports maybeactivated if the corresponding Port reg-
ister iswritten to one. To reduce powerconsumption in sleep mode, it isrecommended
to disablethe pull-ups by writing thePort register to zero before entering sleep.
The XMEM interfacealso provides a buskeeper on theAD7:0 lines.The buskeeper
can be disabled and enabled in softwareasdescribed in “SpecialFunction IO Register –
SFIOR” on page 29. When enabled, the buskeeperwill keep the previous value on the
AD7:0 buswhilethese lines aretri-statedbythe XMEM interface.
If neitherbus-keeper norpull-ups are enabled, the XMEM interface will leave theAD7:0
tri-statedduring a read access until thenextRAM access (internal or external) appears.
Timing External memory deviceshave various timing requirements. To meet these require-
ments, the ATmega8515 XMEM interface providesfourdifferent wait states asshownin
Table 3. Itis important to consider thetimingspecification of theexternal memory
device before selecting the wait state. Themostimportant parameters aretheaccess
D[7:0]
A[7:0]
A[15:8]
RD
WR
SRAM
DQ
G
AD7:0
ALE
A15:8
RD
WR
AVR
(151 paginas)
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