Rainbow-electronics ATmega8515L Manual de usuario descargar pdf (Pagina 144)

144

ATmega8515(L)

2512A–AVR–04/02

Parity Checker TheParityChecker is active when the highUSART Parity mode (UPM1)bit isset. Type

ofparitycheck to be performed(odd or even) isselectedbythe UPM0 bit. When

enabled, the paritycheckercalculates the parity of the data bits in incoming frames and

compares the result with the paritybit from the serialframe. The resultof the check is

stored in the receive buffer togetherwith the receiveddata andstopbits.TheParity

Error(PE) flag can then be readbysoftwaretocheck if the frame had a parity error.

ThePEbit isset if thenext character that can be readfrom the receive bufferhad a par-

ity errorwhen received and the paritychecking was enabled at that point (UPM1 = 1).

Thisbit is valid until the receive buffer(UDR) isread.

Disabling the Receiver In contrasttotheTransmitter, disabling of theReceiverwill beimmediate. Data from

ongoing receptionswill therefore be lost. When disabled(i.e., theRXEN isset to zero)

theReceiverwill no longer overridethenormalfunction of theRxD port pin. The receiver

bufferFIFOwill be flushedwhen theReceiver isdisabled. Remaining data in the buffer

will be lost

Flushing the Receive Buffer The receiverbufferFIFOwill be flushedwhen theReceiver isdisabled(i.e., the buffer

will beemptied of itscontents). Unreaddata will be lost. If the bufferhas to be flushed

during normal operation,due to for instanceanerrorcondition,read the UDR I/Oloca-

tion until theRXC flag iscleared.The following codeexample shows how to flush the

receive buffer.

Note: 1. Theexample codeassumes that the part specificheaderfileis included.

Asynchronous Data

Reception

The USART includes a clock recovery and a data recovery unit forhandling asynchro-

nousdata reception. The clock recovery logic is usedforsynchronizing theinternally

generatedbaudrate clock to theincoming asynchronousserialframes at theRxD pin.

The data recovery logicsamples andlowpass filters each incoming bit, thereby improv-

ing thenoise immunity of the receiver.Theasynchronousreception operationalrange

depends on theaccuracy of theinternalbaudrate clock, the rate of theincoming

frames, and the frame sizeinnumber ofbits.

Assembly Code Example

(1)

USART_Flush:

sbis UCSRA, RXC

ret

in r16, UDR

rjmp USART_Flush

CCode Example

(1)

void USART_Flush( void )

{

unsigned char dummy;

while ( UCSRA & (1<<RXC) ) dummy = UDR;

}

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