Rainbow-electronics ATmega8515L Manual de usuario descargar pdf (Pagina 11)

ATmega8515(L)

2512A–AVR–04/02

Instruction Execution

Timing

Thissection describes the general access timing conceptsfor instruction execution. The

AVR CPU isdriven by the CPUclock clk

CPU

,directly generatedfrom the selectedclock

source for the chip. Nointernalclock division is used.

Figure 6shows the parallel instruction fetches and instruction executions enabledbythe

Harvard architectureand the fast-access Registerfile concept. This is the basicpipelin-

ing concepttoobtain up to 1 MIPSperMHzwith the corresponding unique resultsfor

functionspercost,functionsperclocks, andfunctionsperpower-unit.

Figure 6. TheParallelInstruction Fetches andInstruction Executions

Figure 7shows theinternal timing concept for the Registerfile. Inasingle clock cyclean

ALU operation using two register operands is executed, and the resultisstoredback to

the destination register.

Figure 7. Single CycleALU Operation

Reset and Interrupt

Handling

The AVR providesseveraldifferent interrupt sources.Theseinterrupts and the separate

Reset Vector each have a separate program vector in the program memory space. All

interrupts areassigned individual enable bitswhich must be written logic one together

with the GlobalInterrupt Enable bit in the Status Register in order to enabletheinterrupt.

Dependingonthe program counter value, interrupts maybe automatically disabled

when Boot Lock bitsBLB02 orBLB12 are programmed.Thisfeatureimprovessoftware

security. See the section “Memory Programming” on page 175 fordetails.

The lowestaddresses in the program memory spaceare by default defined as theReset

andInterruptVectors.The complete listof vectors isshownin“Interrupts”onpage 51.

The listalso determines the prioritylevels of the different interrupts.The lower the

address the higher is the prioritylevel.RESET has the highest priority, and nextisINT0

–the ExternalInterruptRequest0.The InterruptVectors can bemoved to the startof

the Boot Flash section by setting the IVSEL bit in the GeneralInterrupt Control Register

(GICR).Refer to “Interrupts”onpage 51 for moreinformation. TheReset Vectorcan

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 222 223

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