7
ATmega8515(L)
2512A–AVR–04/02
The fast-access RegisterFile contains32 x 8-bit generalpurpose working registers with
a single clock cycleaccess time. This allows single-cycleArithmeticLogicUnit (ALU)
operation. Inatypical ALU operation, twooperands areoutput from theRegisterFile,
theoperation is executed, and the resultisstoredback in the RegisterFile – in one
clock cycle.
Six of the 32 registers can beused as three 16-bit indirectaddress registerpointers for
Data Spaceaddressing – enabling efficient address calculations. One of thethese
address pointers can also beused as an address pointerforlook up tables in Flash pro-
gram memory.Theseaddedfunction registers arethe16-bit X-, Y-, andZ-register,
describedlater in thissection.
TheALU supports arithmetic andlogic operationsbetween registers orbetween a con-
stant and a register. Single register operationscan also beexecuted in theALU.After
an arithmetic operation, the Status Register is updated to reflectinformation about the
resultof theoperation.
Program flow isprovidedbyconditional and unconditionaljump andcall instructions,
abletodirectly address the wholeaddress space. Most AVR instructionshave a single
16-bit word format. Every program memory address contains a16- or32-bit instruction.
Program Flash memory spaceisdivided in two sections, the Boot Program section and
theApplication Program section. Bothsectionshave dedicatedLock bitsforwrite and
read/write protection. The SPM instruction that writes into theApplication Flash memory
section must resideinthe Boot Program section.
During interrupts andsubroutine calls, the returnaddress program counter(PC) is
stored on the Stack.The Stack is effectively allocated in thegeneraldata SRAM, and
consequently the stack sizeis only limitedbythetotalSRAMsizeand theusage of the
SRAM.All userprograms mustinitializethe SPinthe reset routine (before subroutines
or interrupts areexecuted).The Stack PointerSPisread/write accessibleinthe I/O
space. The data SRAMcan easily beaccessed through the five different addressing
modessupported in the AVR architecture.
Thememory spaces in theAVRarchitectureareall linear andregular memory maps.
A flexibleinterruptmodule has itscontrolregisters in the I/Ospace with an additional
GlobalInterrupt Enable bit in the Status Register.All interruptshave a separate interrupt
vector in the InterruptVector table. Theinterruptshave priority in accordance with their
InterruptVectorposition. The lower the InterruptVector address, the higher the priority.
The I/O memory space contains64addressesforCPUperipheralfunctions asControl
Registers, SPI, and otherI/Ofunctions.The I/OMemory can beaccesseddirectly, or as
the Data Space locationsfollowing thoseof the RegisterFile,$20 -$5F.
ALU – Arithmetic Logic
Unit
The high-performance AVR ALU operates in direct connection with all the 32general
purpose working registers. Within a single clock cycle, arithmetic operationsbetween
generalpurpose registers orbetween a register and an immediate areexecuted.The
ALU operations are divided into three main categories –arithmetic, logical, andbit-func-
tions. Some implementations of thearchitecturealso provideapowerful multiplier
supporting bothsigned/unsigned multiplication andfractionalformat. See the“Instruc-
tion Set” section for a detaileddescription.
(151 paginas)
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