
26
ATmega8515(L)
2512A–AVR–04/02
Figure 14. ExternalData Memory CycleswithSRWn1 = 0andSRWn0 = 1
(1)
Note: 1. SRWn1 =SRW11 (uppersector) orSRW01 (lowersector), SRWn0 =SRW10 (upper
sector) orSRW00 (lowersector)
TheALE pulseinperiod T5 is only present if thenextinstruction accesses theRAM
(internal or external).
Figure 15. ExternalData Memory CycleswithSRWn1 = 1andSRWn0 = 0
(1)
Note: 1. SRWn1 =SRW11 (uppersector) orSRW01 (lowersector), SRWn0 =SRW10 (upper
sector) orSRW00 (lowersector)
TheALE pulseinperiod T6 is only present if thenextinstruction accesses theRAM
(internal or external).
ALE
T1 T2 T3
Write
Read
WR
T5
A15:8
AddressPrev. Addr.
DA7:0
Address DataPrev. Data XX
RD
DA7:0 (XMBK = 0)
DataPrev. Data Address
DataPrev. Data Address
DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)
T4
ALE
T1 T2 T3
Write
Read
WR
T6
A15:8
AddressPrev. Addr.
DA7:0
Address DataPrev. Data XX
RD
DA7:0 (XMBK = 0)
DataPrev. Data Address
DataPrev. Data Address
DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)
T4 T5
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