Rainbow-electronics ATmega8515L Manual de usuario descargar pdf (Pagina 133)

133

ATmega8515(L)

2512A–AVR–04/02

AVRUSARTvs.AVRUART–

Compatibility

The USART isfully compatible with theAVRUART regarding:

• Bit locations insideall USART Registers

• Baud Rate Generation

•TransmitterOperation

•Transmit BufferFunctionality

•ReceiverOperation

However, the receive buffering has twoimprovements that will affectthe compatibility in

some specialcases:

•Asecondbufferregisterhasbeen added.Thetwo bufferregisters operate as a

circularFIFObuffer.Thereforethe UDRmustonly be read once for each incoming

data. Moreimportant is the factthat theerrorflags(FEandDOR) and theninthdata

bit (RXB8) are bufferedwith the datainthe receive buffer.Thereforethe statusbits

mustalways be readbeforethe UDR Register isread. Otherwisetheerrorstatus

will be lost sincethe bufferstate islost.

•The receiverShift Registercan now actas athird bufferlevel.This isdone by

allowing the receiveddata to remain in the serialShift Register(see Figure 63) if the

bufferregisters are full, until anewstart bit isdetected.The USART is therefore

more resistant to Data OverRun (DOR) errorconditions.

The following controlbitshave changed name,but have same functionality andregister

location:

• CHR9 ischanged to UCSZ2

• ORischanged to DOR

Clock Generation The clock generation logic generates the base clock for theTransmitter and Receiver.

The USART supportsfour modes ofclock operation:Normal asynchronous, Double

Speed asynchronous, Mastersynchronous andSlave synchronous mode. The UMSEL

bit in USART Control andStatus RegisterC(UCSRC) selectsbetween asynchronous

andsynchronous operation. Double Speed(asynchronous modeonly) iscontrolledby

the U2Xfound in the UCSRA Register. When using Synchronous mode (UMSEL = 1),

the Data Direction Registerfor the XCK pin (DDR_XCK) controls whether the clock

sourceis internal(Master mode) or external(Slave mode).The XCK pin is only active

when using Synchronous mode.

Figure 64 shows a block diagram of the clock generation logic.

Figure 64. Clock Generation Logic, Block Diagram

Prescaling

Down-counter

UBRR

/4 /2

fosc

UBRR+1

Sync

OSC

XCK

txclk

U2X

UMSEL

DDR_XCK

xcki

xcko

DDR_XCK

rxclk

Edge

Detector

UCPOL

1 2 ... 128 129 130 131 132 133 134 135 136 137 138 ... 222 223

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