
116
ATmega8515(L)
2512A–AVR–04/02
16-bit Timer/Counter
Register Description
Timer/Counter1 Control
Register A – TCCR1A
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0andCOM1B1:0 control the Output Compare pins(OC1A andOC1B
respectively) behavior. If one orboth of the COM1A1:0 bits are writtentoone, the OC1A
output overrides thenormalport functionality of the I/Opin it isconnected to. If one or
both of the COM1B1:0 bit are written to one, the OC1B output overrides thenormalport
functionality of the I/Opin it isconnected to. However, note that the
Data Direction Reg-
ister
(DDR)bit correspondingtothe OC1A orOC1Bpin must be set in order to enable
the output driver.
When the OC1A orOC1B isconnected to the pin, the function of the COM1x1:0 bits is
dependent of the WGM13:0 bitssetting. Table50shows the COM1x1:0 bit functionality
when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM).
Table51shows the COM1x1:0 bit functionalitywhen the WGM13:0 bits are set to the
fastPWM mode.
Note: 1. A specialcaseoccurs when OCR1A/OCR1B equals TOPandCOM1A1/COM1B1is
set. Inthiscasethe comparematch is ignored, but the set orclear isdone at TOP.
See “FastPWM Mode” on page 108. for more details.
Table52shows the COM1x1:0 bit functionalitywhen the WGM13:0 bits are set to the
phase corrector the phaseandfrequency correct, PWM mode.
Bit 76543 210
COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 TCCR1A
Read/Write R/W R/W R/W R/WW WR/W R/W
Initial Value0 0 0 0 0000
Table 50. Compare Output Mode, non-PWM
COM1A1/
COM1B1
COM1A0/
COM1B0 Description
00Normalportoperation,OC1A/OC1Bdisconnected.
0 1 Toggle OC1A/OC1B on comparematch.
10ClearOC1A/OC1B on comparematch (Set output to lowlevel).
11Set OC1A/OC1B on comparematch (Set output to highlevel).
Table 51. Compare Output Mode,FastPWM
(1)
COM1A1/
COM1B1
COM1A0/
COM1B0 Description
00Normalportoperation,OC1A/OC1Bdisconnected.
01WGM13=0:Normalportoperation,OC1A/OC1Bdisconnected.
WGM13=1: Toggle OC1A on comparematch, OC1Breserved.
10ClearOC1A/OC1B on comparematch, set OC1A/OC1B at TOP.
11Set OC1A/OC1B on comparematch, clearOC1A/OC1B at TOP.
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