Rainbow-electronics ATmega8515L Manual de usuario Pagina 109
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109
ATmega8515(L)
2512A–AVR–04/02
eitherOCR1A orICR1 is usedfordefining theTOPvalue. If one of theinterrupts are
enabled, theinterrupt handlerroutine can beusedfor updating theTOPandcompare
values.
When changing theTOPvalue the program mustensurethat thenew TOPvalue is
higher or equal to thevalue of all of the compare registers. If theTOPvalue islower
than any of the compare registers, a comparematch will never occurbetween the
TCNT1 and the OCR1x. Note that when using fixed TOPvalues theunusedbits are
masked to zero when any of the OCR1x Registers are written.
The procedure for updating ICR1 differs from updating OCR1A when usedfordefining
theTOPvalue. The ICR1 Register is not double buffered.This means that ifICR1 is
changed to a low value when the counter isrunning with none or a lowprescaler value,
thereis a risk that thenewICR1 value written islower than the current value of TCNT1.
The result will then bethat the counterwill miss the comparematch at theTOPvalue.
The counterwill then have to count to the MAX value (0xFFFF) andwrap aroundstart-
ing at 0x0000 beforethe comparematch can occur.The OCR1A Registerhowever, is
double buffered.Thisfeatureallows the OCR1A I/Olocation to be written anytime.
When the OCR1A I/Olocation iswritten thevalue written will be put into the OCR1A
Buffer Register.The OCR1A Compare Registerwill then beupdatedwith thevalue in
the Buffer Register at thenexttimerclock cycletheTCNT1 matches TOP. Theupdate is
done at the same timerclock cycleas theTCNT1 iscleared and theTOV1 flag isset.
Using the ICR1 Registerfordefining TOP works well when using fixed TOPvalues. By
using ICR1, the OCR1A Register isfree to beusedfor generatingaPWM output on
OC1A. However, if the basePWM frequency is actively changed(bychanging theTOP
value), using the OCR1A as TOPisclearly a betterchoice due to itsdouble buffer
feature.
In fastPWM mode, the compareunits allow generation of PWM waveforms on the
OC1xpins. Setting the COM1x1:0 bits to 2 will produceanon-inverted PWM and an
inverted PWM output can begeneratedbysetting the COM1x1:0to3(See Tableon
page 116).TheactualOC1x value will only bevisibleonthe port pin if the data direction
for the port pin isset as output (DDR_OC1x).ThePWM waveformis generatedbyset-
ting (orclearing) the OC1xregister at the comparematch between OCR1x and TCNT1,
andclearing (orsetting) the OC1xregister at thetimerclock cyclethe counter iscleared
(changesfrom TOPtoBOTTOM).
ThePWM frequency for the output can be calculatedbythe following equation:
The N variable represents the prescalerdivider(1, 8,64, 256, or 1024).
Theextreme valuesfor the OCR1x Registerrepresentsspecialcaseswhen generating
aPWM waveform output in the fastPWM mode. If the OCR1x isset equal to BOTTOM
(0x0000) the output will beanarrowspike for each TOP+1timerclock cycle. Setting the
OCR1x equal to TOP will resultinaconstant high orlow output (depending on the polar-
ity of theoutput set by the COM1x1:0 bits.)
A frequency (with 50%duty cycle)waveform output in fastPWM mode can beachieved
by setting OC1A to toggleitslogicallevel on each comparematch (COM1A1:0 = 1).The
waveform generatedwill haveamaximum frequency off
OC
1
A
=f
clk_I/O
/2 when OCR1A is
set to zero (0x0000).Thisfeatureissimilar to the OC1A toggleinCTC mode, exceptthe
double bufferfeatureof the output compare unit is enabled in the fastPWM mode.
f
OCnxPWM
f
clk_I/O
N 1 TOP+()⋅
-----------------------------------=
- Features 1
- ATmega8515(L) 10
- 2512A–AVR–04/02 44
- WATCHDOG 48
- OSCILLATOR 48
- I/O Ports 56
- Ports as General Digital 57
- 8-bit Timer/Counter0 77
- Timer/Counter Clock 78
- OCn Interrupt Flag Set 82
- (COMn1:0 = 1) 82
- 2512A–AVR–04/02 0M 223
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