Rainbow-electronics ATmega8515L Manual de usuario descargar pdf (Pagina 110)

110

ATmega8515(L)

2512A–AVR–04/02

Phase Correct PWM Mode The

phase correct Pulse Width Modulation

orphase correctPWM mode (WGM13:0 = 1,

2,3,10, or 11)provides a highresolution phase correctPWM waveform generation

option. The phase correctPWM modeis, likethe phaseandfrequency correctPWM

mode,based on a dual-slopeoperation. The countercountsrepeatedly from BOTTOM

(0x0000) to TOPand then from TOPtoBOTTOM. In non-inverting compare output

mode, the Output Compare (OC1x) iscleared on the comparematch between TCNT1

andOCR1xwhileupcounting, andset on the comparematch while downcounting. In

inverting Output Comparemode, theoperation is inverted.The dual-slopeoperation has

lower maximum operation frequency than single slopeoperation. However, due to the

symmetricfeatureof the dual-slopePWM modes, thesemodes are preferredfor motor

control applications.

ThePWM resolution for the phase correctPWM mode can be fixed to 8-, 9-, or 10-bit, or

definedbyeitherICR1 orOCR1A. The minimum resolution allowed is 2-bit (ICR1 or

OCR1A set to 0x0003), and themaximum resolution is 16-bit (ICR1 orOCR1A set to

MAX).ThePWM resolution in bitscan be calculatedbyusing the following equation:

In phase correctPWM modethe counter is incremented until the counter value matches

either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or3),the

value in ICR1 (WGM13:0 = 10), or thevalue in OCR1A (WGM13:0 = 11).The counter

has then reached theTOPandchanges the count direction. TheTCNT1 value will be

equal to TOP for one timerclock cycle. The timing diagram for the phase correctPWM

modeisshownonFigure53.The figure shows phase correctPWM mode when OCR1A

orICR1 is used to define TOP. TheTCNT1 value is in thetimingdiagram shownas a

histogram for illustrating the dual-slopeoperation. The diagram includes non-inverted

and inverted PWM outputs.The small horizontalline marks on theTCNT1 slopesrepre-

sent comparematchesbetween OCR1x and TCNT1. The OC1x interrupt flag will be set

when a comparematch occurs.

Figure 53. Phase CorrectPWM Mode, Timing Diagram

PCPWM

TOP 1+()log

2()log

-----------------------------------=

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 2 3 4

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

1 2 ... 105 106 107 108 109 110 111 112 113 114 115 ... 222 223

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