Rainbow-electronics ATmega8515L Manual de usuario descargar pdf (Pagina 22)

ATmega8515(L)

2512A–AVR–04/02

I/O Memory The I/Ospace definition of the ATmega8515 isshown in “RegisterSummary”onpage

209.

All ATmega8515 I/Os andperipherals are placed in the I/Ospace. The I/Olocations are

accessedbythe IN andOUTinstructions, transferring data between the 32 generalpur-

pose working registers and the I/Ospace. I/O Registers within theaddress range $00 -

$1F are directly bit-accessibleusing the SBI andCBIinstructions. Inthese registers, the

value ofsingle bitscan be checkedbyusing the SBIS andSBICinstructions.Refer to

theinstruction set section for more details. When using the I/Ospecificcommands IN

andOUT, the I/O addresses$00 -$3Fmust beused. When addressing I/O Registers as

data spaceusing LD andSTinstructions, $20 must beadded to theseaddresses.

Forcompatibilitywithfuture devices, reservedbitsshould be written to zeroif accessed.

ReservedI/O memory addressesshould neverbe written.

Some of the statusflags are clearedbywriting a logical one to them. Note that the CBI

and SBI instructionswill operate on all bits in the I/O Register, writing a one back into

anyflag read asset, thusclearing the flag. The CBI andSBIinstructionswork withreg-

isters $00 to $1F only.

The I/O andperipherals controlregisters areexplained in latersections.

External Memory

Interface

With all the features the ExternalMemory Interface provides, it iswell suited to operate

as an interfacetomemory devicessuch as externalSRAM andFlash, andperipherals

such as LCD-display, A/D, andD/A. Themainfeatures are:

•

Four Different Wait State Settings (Including No wait State)

• Independent Wait State Setting for Different External Memory Sectors (Configurable

Sector Size)

• The Number of Bits Dedicated to Address High Byte is Selectable

• Bus Keepers on Data Lines to Minimize Current Consumption (Optional)

Overview When theeXternalMEMory (XMEM) is enabled, address space outsidetheinternal

SRAMbecomes availableusing the dedicated external memory pins(see Figure1on

page 2, Table26 on page 63, Table 32onpage 67, and Table 38onpage 71).The

memory configuration isshowninFigure11.

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 222 223

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