Rainbow-electronics W90P710CDG Manual de usuario descargar pdf (Pagina 96)

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W90P710CD/W90P710CDG

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Cache Test Register 1 (CTEST1)

Cache Test Register that will be read back to provide the status of cache RAM BIST. Whether the BIST

is finish and all of bank of SRAM are tested successfully will be presented in this register.

CTEST1

0xFFF6_0004

R Cache test register 1

0x0000_0000

31 30 29 28 27 26 25 24

FINISH RESERVED

23 22 21 20 19 18 17 16

RESERVED

15 14 13 12 11 10 9 8

RESERVED

7 6 5 4 3 2 1 0

BFAIL7 BFAIL6 BFAIL5 BFAIL4 BFAIL3 BFAIL2 BFAIL1 BFAIL0

BITS DESCRIPTION

[31] FINISH

BIST completed

This bit is “0” initially. When BIST mode enabled, this bit will be “1”

after BIST test completed. The values of BFAIL0-7 are valid only

after FINISH = 1.

[30:8] RESERVED

[7] BFAIL7

BIST test fail for data cache tag ram way 1

If this bit equals to “1”, it indicates the data cache tag ram for way

1 is tested fail by BIST. “0” means the test is passed.

[6] BFAIL6

BIST test fail for data cache tag ram way 0

If this bit equals to “1”, it indicates the data cache tag ram for way

0 is tested fail by BIST. “0” means the test is passed.

[5] BFAIL5

BIST test fail for instruction cache tag ram way 1

If this bit equals to “1”, it indicates the instruction cache tag ram for

way 1 is tested fail by BIST. “0” means the test is passed.

[4] BFAIL4

BIST test fail for instruction cache tag ram way 0

If this bit equals to “1”, it indicates the instruction cache tag ram for

way 0 is tested fail by BIST. “0” means the test is passed.

[3] BFAIL3

BIST test fail for data cache ram way 1

If this bit equals to “1”, it indicates the data cache ram for way 1 is

tested fail by BIST. “0” means the test is passed.

1 2 ... 91 92 93 94 95 96 97 98 99 100 101 ... 551 552

Rainbow-electronics W90P710CDG Manual de usuario Pagina 96

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Rainbow-electronics W90P710CDG Manual de usuario Pagina 96

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