
W90P710CD/W90P710CDG
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Timer Interrupt Status Register (TISR)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
TISR
0xFFF8_1018 R/W Timer Interrupt Status Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved TIF1 TIF0
BITS DESCRIPTIONS
[1]
TIF1
Timer Interrupt Flag 1
This bit indicates the interrupt status of Timer channel 1.
0 = It indicates that the Timer 1 dose not countdown to zero yet.
1 = It indicates that the counter of Timer 1 has decremented to zero.
The interrupt flag is set if it was enable.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
[0]
TIF0
Timer Interrupt Flag 0
This bit indicates the interrupt status of Timer channel 0.
0 = It indicates that the Timer 0 dose not countdown to zero yet.
1 = It indicates that the counter of Timer 0 has decremented to zero.
The interrupt flag is set if it was enable.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
Watchdog Timer Control Register (WTCR)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
WTCR
0xFFF8_101C R/W Watchdog Timer Control Register 0x0000_0400
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