Rainbow-electronics W90P710CDG Manual de usuario Pagina 51
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W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 51 - Revision B2
BITS DESCRIPTION
[31:30] PACKAGE
Package Type Select
These two bits are power-on setting latched from pin D[9:8]
Package [31:30] Package Type
1 1 176-pin Package
[29:24] VERSION
Version of chip
[23:0] CHIPID
The chip identifier 0x090.0710
Arbitration Control Register (ARBCON)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
ARBCON
0xFFF0_0004 R/W
Arbitration Control Register
0x0000_0000
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED
7 6 5 4 3 2 1 0
RESERVED IPACT IPEN PRTMOD
BITS DESCRIPTION
[31:3] RESERVED -
[2] IPACT
Interrupt priority active.
When IPEN=”1”, this bit will be set when the ARM core has an
unmasked interrupt request. This bit is available only when the
PRTMOD=0.
[1] IPEN
Interrupt priority enable bit
0 = the ARM core has the lowest priority.
1 = enable to raise the ARM core priority to second
This bit is available only when the PRTMOD=0.
[0] PRTMOD
Priority mode select
0 = Fixed Priority Mode (default)
1 = Rotate Priority Mode
- W90P710CD/W90P710CDG 1
- Product Data Sheet 1
- - - 1 -- None None 343
- [23:16] 366
- RTCVDD1.8V 439
- Continued 485
- [31:24] 488
- [15:8] 488
- EMC Registers Map, continued 535
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