Rainbow-electronics W90P710CDG Manual de usuario descargar pdf (Pagina 148)

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101

W90P710CD/W90P710CDG

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MRPC 0xFFF0_30BC R MAC Receive Pause Count Register 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

MRPC

7 6 5 4 3 2 1 0

MRPC

BITS DESCRIPTIONS

[31:16] Reserved -

[15:0] MRPC

The MAC Receive Pause Count keeps the operand field of the

PAUSE control frame. It indicates how many slot time (512 bit time)

the Tx of EMC will be paused.

MAC Receive Pause Current Count Register (MRPCC)

The EMC of W90P710 supports the PAUSE control frame reception and recognition. If EMC received

a PAUSE control frame, the operand field of the PAUSE control frame will be extracted and stored into

a down count timer. The MRPCC shows the current value of that down count timer for S/W to know

how long the Tx of EMC will be paused. The MRPCC is read only and write to this register has no

effect.

MRPCC 0xFFF0_30C0 R

MAC Receive Pause Current Count

0x0000_0000

1 2 ... 143 144 145 146 147 148 149 150 151 152 153 ... 551 552

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Rainbow-electronics W90P710CDG Manual de usuario Pagina 148

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