
W90P710CD/W90P710CDG
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BITS DESCRIPTIONS
[31:2] Reserved
[1] USB_DPS
USB Bus D+ Signal Status
0: USB Bus D+ Signal is low
1: USB Bus D+ Signal is high
[0] USB_DMS
USB Bus D- Signal Status
0: USB Bus D- Signal is low
1: USB Bus D- Signal is high
USB Engine Register (USB_ENG)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
USB_ENG 0xFFF0603C R/W USB Engine Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved SDO_RD CV_LDA CV_STL CV_DAT
BITS DESCRIPTIONS
[31:4] Reserved
[3] SDO_RD
Setup or Bulk-Out Data Read Control
0: NO Operation
1: Read Setup or Bulk-Out Data from USB Host
NOTE: this bit will auto clear after 32 HCLK
[2] CV_LDA
USB Class and Vendor Command Last Data Packet Control
0: NO Operation
1: Last Data Packet for Data Input of Class and Vendor Command
NOTE: this bit will auto clear after 32 HCLK
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