
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 407 - Revision B2
GPIO Port3 Data Input Register (GPIO_DATAIN3)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
GPIO_DATAIN3 0xFFF8_303C R/W GPIO port3 data input register 0xXXXX_XXXX
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED
7 6 5 4 3 2 1 0
DATAIN3[7:0]
BITS DESCRIPTION
[31:8] RESERVED
-
[7:0]
DATAIN3
Port3 input data register
The DATAIN3 indicates the status of each GPIO67~GPIO60 pin
regardless of its operation mode. The reserved bits will be read as
0s.
GPIO Port4 Configuration Register (GPIO_CFG4)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
GPIO_CFG4 0xFFF8_3040 R/W GPIO port4 configuration register 0x0015_5555
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED PT4CFG10 PT4CFG9 PT4CFG8
15 14 13 12 11 10 9 8
PT4CFG7 PT4CFG6 PT4CFG5 PT4CFG4
7 6 5 4 3 2 1 0
PT4CFG3 PT4CFG2 PT4CFG1 PT4CFG0
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