
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 437 - Revision B2
Continued
BITS DESCRIPTIONS
[0]
Alarm_int_st
RTC Alarm Interrupt Indication REGISTER
1 = It indicates that time counter and calendar counter have
counted
to a specified time recorded in TAR and CAR. RTC alarm
interrupt
has been activated.
0 = It indicates that alarm interrupt has never occurred. Software
can
Also clear this bit after RTC interrupt has occurred.
Note : User can clear these two bits by writing 0x0 to RIIR
RTC Tick Time Register (RTC_TTR)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
RTC_TTR 0xFFF8_4030 R/W RTC Tick Time Register 0X0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved TTI
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