
W90P710CD/W90P710CDG
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SD global Interrupt Status Register (SDGISR)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
SDGISR
0xFFF0_7010
R/W SD Global Interrupt Status Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved
ERRINT DRdINT DWrINT SDHIINT Reserved Reserved SDGINT
BITS DESCRIPTIONS
[31:7]
Reserved -
[6]
ERRINT Bus Error Interrupt Status
[5]
DRdINT
DMA Read Interrupt Status
This bit indicates the DMA read transfer (from external SDRAM to
internal buffer) has finished.
1’b0: No DMA read transfer completion
1’b1: DMA read transfer completed
[4]
DWrINT
DMA Write Interrupt Status
This bit indicates the DMA write transfer (from internal buffer to external
SDRAM) has finished.
1’b0: No DMA write transfer completion
1’b1: DMA write transfer completed
[3]
SDHIINT
Secure Digital Host Controller Interface Interrupt Status
This bit indicates there is an interrupt status from Secure Digital host
controller.
1’b0: No interrupt status from Secure Digital host controller interface.
1’b1: There is an interrupt status from Secure Digital host controller
Interface
[0]
SDGINT
SD Host Global Interrupt Status
This bit is the wired-OR of SDHINT, DWrINT and DRdINT.
1’b0: No SD host controller interrupt notification
1’b1: There is an SD host controller interrupt status
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