
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 465 - Revision B2
Smart Card Host Buffer Time-Out Data Register (SCHI_BTOR)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
SCHI_BTOR0 0XFFF8_5044
R/W
Buffer Time out Data Register 0 0x0000_0000
SCHI_BTOR1 0XFFF8_5844
R/W
Buffer Time out Data Register 1 0x0000_0000
BITS DESCRIPTIONS
[31:8]
RESERVED -
[7]
BTOIE
Buffer Time Out Interrupt Enable
The feature of receiver buffer time out interrupt is enabled only
when BTOIE[7] = ERDRI =1 .
[6:0]
BTOIC
Buffer Time Out Interrupt Comparator
The time out counter resets and starts counting (the counting clock
= ETU) whenever the RX FIFO receives a new data word. Once
the content of time out counter (TOUT_CNT) is equal to that of
time out interrupt comparator (TOIC), a receiver time out interrupt
(Irpt_TOUT) is generated if TOR[7] = ERDRI =1. A new incoming
data word or BRX FIFO empty clear Irpt_TOUT.
Smart Card Host Baud Rate Divider Latch Lower Byte (SCHI_BLL)
REGISTER ADDRESS R/W DESCRIPTION
RESET
VALUE
SCHI_BLL0
0XFFF8_5000
(DLAB = 1)
R/W
Baud rate divisor Latch Lower byte Register 0 0x0000_001F
SCHI_BLL1
0XFFF8_5800
(DLAB = 1)
R/W
Baud rate divisor Latch Lower byte Register 1 0x0000_001F
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED
7 6 5 4 3 2 1 0
BTOIE BTOIC_6 BTOIC_5 BTOIC_4 BTOIC_3 BTOIC_2 BTOIC_1 BTOIC_0
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