
W90P710CD/W90P710CDG
- 74 -
Fig 6.3.3 ROM/FLASH Page Read Operation Timing
Configuration Registers(SDCONF0/1)
The configuration registers enable software to set a number of operating parameters for the SDRAM
controller. There are two configuration registers SDCONF0、SDCONF1 for SDRAM bank 0、bank 1
respectively. Each bank can have a different configuration.
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
SDCONF0 0xFFF0_1008 R/W SDRAM bank 0 configuration register 0x0000_0800
SDCONF1 0xFFF0_100C R/W SDRAM bank 1 configuration register 0x0000_0800
31 30 29 28 27 26 25 24
BASADDR
23 22 21 20 19 18 17 16
BASADDR RESERVED
15 14 13 12 11 10 9 8
MRSET RESERVED AUTOPR LATENCY RESERVED
7 6 5 4 3 2 1 0
COMPBK DBWD COLUMN SIZE
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