Rainbow-electronics W90P710CDG Manual de usuario descargar pdf (Pagina 489)

100

101

W90P710CD/W90P710CDG

- 490 -

31 30 29 28 27 26 25 24

Tx [31:24]

23 22 21 20 19 18 17 16

Tx [23:16]

15 14 13 12 11 10 9 8

Tx [15:8]

7 6 5 4 3 2 1 0

Tx [7:0]

BITS DESCRIPTIONS

[31:0]

Data Transmit Register

The Data Transmit Registers hold the data to be transmitted in the next

transfer. Valid bits depend on the transmit bit length field in the CNTRL

CNTRL[Tx_NUM] is set to 0x0, the bit Tx0[7:0] will be transmitted in next

transfer. If CNTRL[Tx_BIT_LEN] is set to 0x00 and CNTRL[Tx_NUM] is

set to 0x3, the core will perform four 32-bit transmit/receive successive

using the same setting (the order is Tx0[31:0], Tx1[31:0], Tx2[31:0],

Tx3[31:0]).

NOTE: The RxX and TxX registers share the same flip-flops, which

means that what is received from the input data line in one transfer will

be transmitted on the output data line in the next transfer if no write

access to the TxX register is executed between the transfers.

1 2 ... 484 485 486 487 488 489 490 491 492 493 494 ... 551 552

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Rainbow-electronics W90P710CDG Manual de usuario Pagina 489

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