Rainbow-electronics W90P710CDG Manual de usuario Pagina 482

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W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 483 - Revision B2
6.19 Universal Serial Interface
The USI is a synchronous serial interface performs a serial-to-parallel conversion on data characters
received from the peripheral, and a parallel-to-serial conversion on data characters received from
CPU. This interface can drive one external peripherals and is seen as the master. It can generate an
interrupt signal when data transfer is finished and can be cleared by writing 1 to the interrupt flag. The
active level of device/slave select signal can be chosen to low active or high active, which depends on
the peripheral it’s connected. Writing a divisor into DIVIDER register can program the frequency of
serial clock output. This master core contains four 32-bit transmit/receive buffers, and can provide
burst mode operation. The maximum bits can be transmitted/received is 32 bits, and can
transmit/receive data up to four times successive.
The USI (Microwire/SPI) Master Core includes the following features:
AMBA APB interface compatible
Support USI (Microwire/SPI) master mode
Full duplex synchronous serial data transfer
Variable length of transfer word up to 32 bits
Provide burst mode operation, transmit/receive can be executed up to four times in one transfer
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
1 slave/device select lines
Fully static synchronous design with one clock domain
6.19.1 USI Timing Diagram
The timing diagram of USI is shown as following.
MSB
(Tx[7])
LSB
(Tx[0])
MSB
(Rx[7])
LSB
(Rx[0])
mw_ss_o
mw_sclk_o
mw_so_o
mw_si_i
CNTRL[LSB]=0, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08,
CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0, SSR[SS_LVL]=0
Tx[6] Tx[5] Tx[4] Tx[3] Tx[2] Tx[1]
Rx[6] Rx[5] Rx[4] Rx[3] Rx[2] Rx[1]
Fig. 6.19.1.1 USI Timing
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