Rainbow-electronics ATmega161L Manual de usuario descargar pdf (Pagina 56)

ATmega161(L)

1228C–AVR–08/02

Note: 1. X = A or B

Note that in the PWM mode, the 8, 9 or 10 least significant OCR1A/OCR1B bits

(depends of resolution), when written, are transferred to a temporary location. They are

latched when Timer/Counter1 reaches the value TOP. This prevents the occurrence of

odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B

write. See Figure 37 and Figure 38 for an example in each mode.

Figure 37. Effects on Unsynchronized OCR1 Latching

(1)

Note: 1. Note: X = A or B

Table 18. Compare1 Mode Select in PWM Mode

(1)

CTC1 COM1X1 COM1X0 Effect on OCX1

0 0 0 Not connected

0 0 1 Not connected

01 0

Cleared on compare match, up-counting. Set on compare

match, down-counting (non-inverted PWM).

01 1

Cleared on compare match, down-counting. Set on compare

match, up-counting (inverted PWM).

1 0 0 Not connected

1 0 1 Not connected

1 1 0 Cleared on compare match, set on overflow.

1 1 1 Set on compare match, cleared on overflow.

Counter

alue

Compare V

alue

PWM

Output OC1X

Synchronized OCR1X Latch

Counter

Value

Compare Value

PWM Output OC1X

Unsynchronized OCR1X Latch

Glitch

Compare Value changes

Compare V

alue changes

1 2 ... 51 52 53 54 55 56 57 58 59 60 61 ... 158 159

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Rainbow-electronics ATmega161L Manual de usuario Pagina 56