33
ATmega161(L)
1228C–AVR–08/02
Timer/Counter Interrupt Flag
Register – TIFR
• Bit 7
– TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding Interrupt Handling Vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the Flag. When the I-bit in SREG, and TOIE1
(Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the
Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when
Timer/Counter1 changes counting direction at $0000.
• Bit 6
– OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when a compare match occurs between the Timer/Counter1
and the data in OCR1A (Output Compare Register 1A). OCF1A is cleared by hardware
when executing the corresponding Interrupt Handling Vector. Alternatively, OCF1A is
cleared by writing a logical “1” to the Flag. When the I-bit in SREG and OCIE1A
(Timer/Counter1 Compare Match Interrupt A Enable) and OCF1A are set (one), the
Timer/Counter1 Compare A Match Interrupt is executed.
• Bit 5
– OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when a compare match occurs between the Timer/Counter1
and the data in OCR1B (Output Compare Register 1B). OCF1B is cleared by hardware
when executing the corresponding Interrupt Handling Vector. Alternatively, OCF1B is
cleared by writing a logical “1” to the Flag. When the I-bit in SREG and OCIE1B
(Timer/Counter1 Compare Match Interrupt B Enable) and OCF1B are set (one), the
Timer/Counter1 Compare B Match Interrupt is executed.
• Bit 4
– TOV2: Timer/Counter2 Overflow Flag
The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding Interrupt Handling Vector. Alternatively,
TOV2isclearedbywritingalogical“1” to the Flag. When the SREG I-bit and TOIE2
(Timer/Counter2 Overflow Interrupt Enable) and TOV2 are set (one), the
Timer/Counter2 Overflow interrupt is executed.
• Bit 3
– ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an Input Capture Event, indicating that the
Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1
is cleared by hardware when executing the corresponding Interrupt Handling Vector.
Alternatively, ICF1 is cleared by writing a logical “1” to the Flag. When the SREG I-bit
and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the
Timer/Counter1 Capture Interrupt is executed.
• Bit 2
– OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2
and the data in OCR2 (Output Compare Register 2). OCF2 is cleared by hardware when
executing the corresponding Interrupt Handling Vector. Alternatively, OCF2 is cleared
by writing a logical “1” to the Flag. When the I-bit in SREG and OCIE2 (Timer/Counter2
Bit 76543210
$38 ($58) TOV1 OCF1A OCIFB TOV2 ICF1 OCF2 TOV0 OCF0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
InitialValue00000000
(54 paginas)
(14 paginas)
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