Rainbow-electronics AT89C51RC Manual de usuario

1PLCC78910111213141516173938373635343332313029P1.5P1.6P1.7RST(RXD) P3.0NC(TXD) P3.1(INT0) P3.2(INT1) P3.3(T0) P3.4(T1) P3.5P0.4 (AD4)P0.5 (AD5)P0.6 (A

AT89C51RC10Figure 3. Timer 2 Auto Reload Mode (DCEN = 0)OSCEXF2TF2T2EX PINT2 PINTR2EXEN2C/T2 = 0C/T2 = 1CONTR OLRELOADCONTROLTRANSITIONDETECTOR

AT89C51RC11Figure 4. Timer 2 Auto Reload Mode (DCEN = 1)Figure 5. Timer 2 in Baud Rate Generator ModeOSCEXF2TF2T2EX PINCOUNTDIRECTION1=UP0=DOT2 PI

AT89C51RC12Baud Rate GeneratorTimer 2 is selected as the baud rate generator by settingTCLK and/or RCLK in T2CON (Table 2). Note that thebaud rates fo

AT89C51RC13Programmable Clock OutA 50% duty cycle clock can be programmed to come out onP1.0, as shown in Figure 6. This pin, besides being a regu-lar

AT89C51RC14Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier that can be configured for use a

AT89C51RC15Program Memory Lock BitsThe AT89C51RC has three lock bits that can be left unpro-grammed (U) or can be programmed (P) to obtain the addi-ti

AT89C51RC16Programming InterfaceEvery code byte in the Flash array can be programmed byusing the appropriate combination of control signals. Thewrite

AT89C51RC17Flash Programming and Verification Waveforms Flash Programming and Verification CharacteristicsTA = 20°C to 30°C, VCC = 4.5V to 5.5VSymbol

AT89C51RC18Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:Maximum IOL per port pin: 10 mAMaximum I

AT89C51RC19AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all otheroutp

AT89C51RC2pinout. The on-chip Flash allows the program memory tobe user programmed by a conventional nonvolatile memoryprogrammer. A total of 512 byte

AT89C51RC20External Program Memory Read CycleExternal Data Memory Read CycletLHLLtLLIVtPLIVtLLAXtPXIZtPLPHtPLAZtPXAVtAVLLtLLPLtAVIVtPXIXALEPSENPORT 0P

AT89C51RC21External Data Memory Write CycleExternal Clock Drive WaveformstLHLLtLLWLtLLAXtWHLHtAVLLtWLWHtAVWLtQVWXtQVWHtWHQXA0 - A7 FROM RI OR DP

AT89C51RC22Shift Register Mode Timing WaveformsAC Testing Input/Output Waveforms(1)Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a lo

AT89C51RC23Note: Shaded area indicates preliminary availability.Ordering InformationSpeed (MHz)PowerSupply Ordering Code Package Operation Range24 4.0

AT89C51RC24Packaging Information*Controlling dimension: millimeters1.20(0.047) MAX10.10(0.394)9.90(0.386)SQ12.21(0.478)11.75(0.458)SQ0.75(0.030)0.45(0

© Atmel Corporation 2000.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

AT89C51RC3The AT89C51RC provides the following standard features:32K bytes of Flash, 512 bytes of RAM, 32 I/O lines, three16-bit timer/counters, a six

AT89C51RC4memory. This pin is also the program pulse input (PROG)during Flash programming. In normal operation, ALE is emitted at a constant rate of 1

AT89C51RC5Special Function RegistersA map of the on-chip memory area called the Special Func-tion Register (SFR) space is shown in Table 1.Note that n

AT89C51RC6Dual Data Pointer Registers: To facilitate accessing bothinternal and external data memory, two banks of 16-bitData Pointer Registers are pr

AT89C51RC7Memory OrganizationMCS-51 devices have a separate address space for Pro-gram and Data Memory. Up to 64K bytes each of externalProgram and Da

AT89C51RC8Hardware Watchdog Timer (One-time Enabled with Reset-out)The WDT is intended as a recovery method in situationswhere the CPU may be subjecte

AT89C51RC9the transition was detected. Since two machine cycles (24oscillator periods) are required to recognize a 1-to-0 transi-tion, the maximum cou