Rainbow-electronics ATmega161L Manual de usuario descargar pdf (Pagina 133)

133

ATmega161(L)

1228C–AVR–08/02

External Data Memory Timing

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 51. External Data Memory Characteristics, 4.0 - 5.5 Volts, No Wait State

Symbol Parameter

8 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL

Oscillator Frequency 0.0 8.0 MHz

LHLL

ALE Pulse Width 95 1.0t

CLCL

-30 ns

AVLL

Address Valid A to ALE Low 22.5 0.5t

CLCL

-40

(1)

3a t

LLAX_ST

Address Hold After ALE Low,

write access

10 10 ns

3b t

LLAX_LD

Address Hold after ALE Low,

read access

15 15 ns

AVLLC

Address Valid C to ALE Low 22.5 0.5t

CLCL

-40

(1)

AVR L

Address Valid to RD Low 95 1.0t

CLCL

-30 ns

AVWL

Address Valid to WR Low 95 1.0t

CLCL

-30 ns

LLWL

ALE Low to WR Low 42.5 145 0.5t

CLCL

-20

(2)

0.5t

CLCL

+20

(2)

LLRL

ALE Low to RD Low 42.5 145 0.5t

CLCL

-20

(2)

0.5t

CLCL

+20

(2)

DVRH

Data Setup to RD High 60 60 ns

10 t

RLDV

Read Low to Data Valid 65 65 ns

11 t

RHDX

Data Hold After RD High 0 0 ns

12 t

RLRH

RD Pulse Width 105 1.0t

CLCL

-20 ns

13 t

DVWL

Data Setup to WR Low 27.5 0.5t

CLCL

-35

(1)

14 t

WHDX

Data Hold After WR High 27.5 0.5t

CLCL

-35

(1)

15 t

DVWH

Data Valid to WR High 95 1.0t

CLCL

-30 ns

16 t

WLWH

WR Pulse Width 105 1.0t

CLCL

-20 ns

Table 52. External Data Memory Characteristics, 4.0 - 5.5 Volts, 1 Cycle Wait State

Symbol Parameter

8 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL

Oscillator Frequency 0.0 8.0 MHz

10 t

RLDV

Read Low to Data Valid 185 2.0t

CLCL

-65 ns

12 t

RLRH

RD Pulse Width 230 2.0t

CLCL

-20 ns

15 t

DVWH

Data Valid to WR High 220 2.0t

CLCL

-30 ns

16 t

WLWH

WR Pulse Width 230 2.0t

CLCL

-20 ns

1 2 ... 128 129 130 131 132 133 134 135 136 137 138 ... 158 159

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