
135
ATmega161(L)
1228C–AVR–08/02
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
12 t
RLRH
RD Pulse Width 230 1.0t
CLCL
-20 ns
13 t
DVWL
Data Setup to WR Low 70 0.5t
CLCL
-55 ns
14 t
WHDX
Data Hold After WR High 125 0.5t
CLCL
-0 ns
15 t
DVWH
Data Valid to WR High 210 1.0t
CLCL
-40 ns
16 t
WLWH
WR Pulse Width 230 1.0t
CLCL
-20 ns
Table 55. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait State (Continued)
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
Table 56. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL
Oscillator Frequency 0.0 4.0 MHz
10 t
RLDV
Read Low to Data Valid 335 2.0t
CLCL
-165 ns
12 t
RLRH
RD Pulse Width 480 2.0t
CLCL
-20 ns
15 t
DVWH
Data Valid to WR High 460 2.0t
CLCL
-40 ns
16 t
WLWH
WR Pulse Width 480 2.0t
CLCL
-20 ns
Table 57. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL
Oscillator Frequency 0.0 4.0 MHz
10 t
RLDV
Read Low to Data Valid 585 3.0t
CLCL
-165 ns
12 t
RLRH
RD Pulse Width 730 3.0t
CLCL
-20 ns
15 t
DVWH
Data Valid to WR High 710 3.0t
CLCL
-40 ns
16 t
WLWH
WR Pulse Width 730 3.0t
CLCL
-20 ns
Table 58. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL
Oscillator Frequency 0.0 4.0 MHz
10 t
RLDV
Read Low to Data Valid 585 3.0t
CLCL
-165 ns
12 t
RLRH
RD Pulse Width 730 3.0t
CLCL
-20 ns
14 t
WHDX
Data Hold After WR High 375 1.5t
CLCL
-0 ns
15 t
DVWH
Data Valid to WR High 710 3.0t
CLCL
-40 ns
16 t
WLWH
WR Pulse Width 730 3.0t
CLCL
-20 ns
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