
103
ATmega161(L)
1228C–AVR–08/02
Figure 66. Port D Schematic Diagram (Pins PD2 and PD3)
Figure 67. Port D Schematic Diagram (Pin PD4)
WP:
WD:
RL:
RP:
RD:
n:
m:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
2, 3
0, 1
DA
TA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PD4
R
R
WP:
WD:
RL:
RP:
RD:
AS2:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
ASYNCH SELECT T/C2
DDD4
PORTD4
RL
RP
AS2
T/C2 OSC
AMP INPUT
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