
82
ATmega128(L)
2467B–09/01
Port B Input Pins Address –
PINB
Port C Data Register – PORTC
Port C Data Direction Register
– DDRC
Port C Input Pins Address –
PINC
In ATmega103 compatibility mode, DDRC and PINC registers are initialized to being
Push-Pull Zero Output. The port pins assumes their initial value, even if the clock is not
running. Note that the DDRC and PINC registers are available in ATmega103 compati-
bility mode, and should not be used for 100% back-ward compatibility.
Port D Data Register – PORTD
Port D Data Direction Register
– DDRD
Port D Input Pins Address –
PIND
Port E Data Register – PORTE
Bit 76543210
PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB
Read/WriteRRRRRRRR
Initial value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 76543210
DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 76543210
PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC
Read/WriteRRRRRRRR
Initial value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 76543210
DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 76543210
PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND
Read/WriteRRRRRRRR
Initial value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 PORTE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
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