Rev. 4136A–USB–03/03 Features• 80C52X2 Core (6 Clocks per Instruction)– Maximum Core Frequency 40 MHz in X1 Mode– Dual Data Pointer– Full-duplex Enha

10AT89C51314136A–USB–03/03Table 10. System Signal DescriptionSignal Name Type DescriptionAlternate FunctionAD[7:0] I/OMultiplexed Address/Data LSB fo

100AT89C51314136A–USB–03/03Power Reduction Mode P1 inputs allow exit from idle and power down modes as detailed in section “Power-down Mode”.Registers

101AT89C51314136A–USB–03/03Table 73. KBE RegisterKBE - Keyboard Input Enable Register (9Dh)Reset Value = 0000 0000b76543210KBE7 KBE6 KBE5 KBE4 KBE3 K

102AT89C51314136A–USB–03/03Table 74. KBLS RegisterKBLS-Keyboard Level Selector Register (9Ch)Reset Value = 0000 0000b76543210KBLS7 KBLS6 KBLS5 KBLS4

103AT89C51314136A–USB–03/03Programmable LED AT89C5131 have up to 4 programmable LED current sources, configured by the regis-ter LEDCON.Reset Value =

104AT89C51314136A–USB–03/03Serial Peripheral Interface (SPI)The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serialcommun

105AT89C51314136A–USB–03/03pins (Figure 42). To prevent bus conflicts on the MISO line, only one slave should beselected at a time by the Master for a

106AT89C51314136A–USB–03/03Functional Description Figure 43 shows a detailed structure of the SPI module. Figure 43. SPI Module Block DiagramOperatin

107AT89C51314136A–USB–03/03Figure 44. Full-duplex Master/Slave InterconnectionMaster Mode The SPI operates in Master mode when the Master bit, MSTR (

108AT89C51314136A–USB–03/03Figure 45. Data Transmission Format (CPHA = 0)Figure 46. Data Transmission Format (CPHA = 1)Figure 47. CPHA/SS TimingAs

109AT89C51314136A–USB–03/03Error Conditions The following flags in the SPSTA signal SPI error conditions:Mode Fault (MODF) Mode Fault error in Master

11AT89C51314136A–USB–03/03VREF PWR3V Voltage ReferenceVREF is used to supply the on-chip USB differential drivers.It is internally connected to the on

110AT89C51314136A–USB–03/03Figure 48. SPI Interrupt Requests GenerationRegisters There are three registers in the module that provide control, status

111AT89C51314136A–USB–03/03Reset Value = 0001 0100bNot bit addressableSerial Peripheral Status Register (SPSTA)The Serial Peripheral Status Register c

112AT89C51314136A–USB–03/03Reset Value = 00X0 XXXXbNot Bit addressableSerial Peripheral Data Register (SPDAT)The Serial Peripheral Data Register (Tabl

113AT89C51314136A–USB–03/03USB ControllerIntroduction The AT89C5131 implements a USB device controller supporting full speed data trans-fer. In additi

114AT89C51314136A–USB–03/03USB Device Firmware Upgrade (DFU)The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chipFlash memo

115AT89C51314136A–USB–03/03Serial Interface Engine (SIE) The SIE performs the following functions:• NRZI data encoding and decoding.• Bit stuffing and

116AT89C51314136A–USB–03/03Function Interface Unit (FIU) The Function Interface Unit provides the interface between the AT89C5131 and the SIE.It manag

117AT89C51314136A–USB–03/03ConfigurationGeneral Configuration • USB controller enableBefore any USB transaction, the 48 MHz required by the USB contro

118AT89C51314136A–USB–03/03• Endpoint enableBefore using an endpoint, this one will be enabled by setting the EPEN bit in theUEPCONX register.An endpo

119AT89C51314136A–USB–03/03• Endpoint FIFO resetBefore using an endpoint, its FIFO will be reset. This action resets the FIFO pointerto its original v

12AT89C51314136A–USB–03/03SFR Mapping The Special Function Registers (SFRs) of the AT89C5131 fall into the followingcategories:• C51 core registers: A

120AT89C51314136A–USB–03/03Bulk/Interrupt TransactionsBulk and Interrupt transactions are managed in the same way.Bulk/Interrupt OUT Transactions in S

121AT89C51314136A–USB–03/03Bulk/Interrupt OUT Transactions in Ping-pong ModeFigure 56. Bulk/Interrupt OUT Transactions in Ping-pong ModeAn endpoint w

122AT89C51314136A–USB–03/03Bulk/Interrupt IN Transactions in Standard ModeFigure 57. Bulk/Interrupt IN Transactions in Standard ModeAn endpoint will

123AT89C51314136A–USB–03/03Bulk/Interrupt IN Transactions in Ping-pong ModeFigure 58. Bulk/Interrupt IN Transactions in Ping-pong ModeAn endpoint wil

124AT89C51314136A–USB–03/03Control TransactionsSetup Stage The DIR bit in the UEPSTAX register will be at 0.Receiving Setup packets is the same as rec

125AT89C51314136A–USB–03/03Isochronous TransactionsIsochronous OUT Transactions in Standard ModeAn endpoint will be first enabled and configured befor

126AT89C51314136A–USB–03/03If the Host sends more bytes than supported by the endpoint FIFO, the overflow datawon’t be stored, but the USB controller

127AT89C51314136A–USB–03/03MiscellaneousUSB Reset The EORINT bit in the USBINT register is set by hardware when a End Of Reset hasbeen detected on the

128AT89C51314136A–USB–03/03Suspend/Resume ManagementSuspend The Suspend state can be detected by the USB controller if all the clocks are enabledand i

129AT89C51314136A–USB–03/03Upstream Resume A USB device can be allowed by the Host to send an upstream resume for RemoteWake Up purpose.When the USB c

13AT89C51314136A–USB–03/03The table below shows all SFRs with their address and their reset value.Note: 1. FCON access is reserved for the Flash API a

130AT89C51314136A–USB–03/03Detach Simulation In order to be re-enumerated by the Host, the AT89C5131 has the possibility to simulatea DETACH - ATTACH

131AT89C51314136A–USB–03/03Table 82. Priority LevelsUSB Interrupt Control System As shown in Figure 64, many events can produce a USB interrupt:• TXC

132AT89C51314136A–USB–03/03Figure 64. USB Interrupt Control Block DiagramTXCMPUEPSTAX.0RXOUTB0UEPSTAX.1RXSETUPUEPSTAX.2STLCRCUEPSTAX.3EPXIEUEPIEN.XEP

133AT89C51314136A–USB–03/03USB Registers Table 83. USBCON RegisterUSBCON (S:BCh)USB Global Control RegisterReset Value = 00h76543210USBE SUSPCLK SDRM

134AT89C51314136A–USB–03/03Table 84. USBINT RegisterUSBINT (S:BDh)USB Global Interrupt RegisterReset Value = 00h76543210- - WUPCPU EORINT SOFINT - -

135AT89C51314136A–USB–03/03Table 85. USBIEN RegisterUSBIEN (S:BEh)USB Global Interrupt Enable RegisterReset Value = 10hTable 86. USBADDR RegisterUSB

136AT89C51314136A–USB–03/03Table 87. UEPNUM RegisterUEPNUM (S:C7h)USB Endpoint NumberReset Value = 00h76543210----EPNUM3EPNUM2EPNUM1EPNUM0Bit Number

137AT89C51314136A–USB–03/03Table 88. UEPCONX RegisterUEPCONX (S:D4h)USB Endpoint X Control Register Note: 1. (X = EPNUM set in UEPNUM Register UEPNUM

138AT89C51314136A–USB–03/03Reset Value = 00hTable 89. UEPSTAX (S:CEh) USB Endpoint X Status Register76543210DIR RXOUTB1 STALLRQ TXRDY STL/CRC RXSETUP

139AT89C51314136A–USB–03/03Table 90. UEPDATX RegisterUEPDATX (S:CFh)USB FIFO Data Endpoint X (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h)USB Endp

14AT89C51314136A–USB–03/03The Special Function Registers (SFRs) of the AT89C5131 fall into the followingcategories:Table 13. C51 Core SFRsTable 14.

140AT89C51314136A–USB–03/03Table 92. UBYCTHX RegisterUBYCTHX (S:E3h)USB Byte Count High Register X (X = EPNUM set in UEPNUM Register UEPNUM(S:C7h) US

141AT89C51314136A–USB–03/03Table 93. UEPRST RegisterUEPRST (S:D5h)USB Endpoint FIFO Reset RegisterReset Value = 00h76543210- EP6RST EP5RST EP4RST EP3

142AT89C51314136A–USB–03/03Table 94. UEPINT RegisterUEPINT (S:F8h read-only)USB Endpoint Interrupt RegisterReset Value = 00h76543210- EP6INT EP5INT E

143AT89C51314136A–USB–03/03Table 95. UEPIEN RegisterUEPIEN (S:C2h)USB Endpoint Interrupt Enable RegisterReset Value = 00h76543210- EP6INTE EP5INTE EP

144AT89C51314136A–USB–03/03Table 96. UFNUMH RegisterUFNUMH (S:BBh, read-only)USB Frame Number High RegisterReset Value = 00hTable 97. UFNUML Registe

145AT89C51314136A–USB–03/03Power ManagementIdle Mode An instruction that sets PCON.0 indicates that it is the last instruction to be executedbefore go

146AT89C51314136A–USB–03/03Figure 65. Power-down Exit WaveformExit from power-down by reset redefines all the SFRs, exit from power-down by externali

147AT89C51314136A–USB–03/03Registers Table 99. PCON RegisterPCON (S:87h)Power Control RegisterReset Value = 10h76543210SMOD1 SMOD0 - POF GF1 GF0 PD I

148AT89C51314136A–USB–03/03Hardware Watchdog TimerThe WDT is intended as a recovery method in situations where the CPU may be sub-jected to software u

149AT89C51314136A–USB–03/03Table 101. WDTPRG RegisterWDTPRG - Watchdog Timer Out Register (0A7h)Reset value = XXXX X000WDT During Power-down and Idle

15AT89C51314136A–USB–03/03Table 15. Timer SFR’s MnemonicAddName 76543210TH0 8Ch Timer/Counter 0 High byteTL0 8Ah Timer/Counter 0 Low byteTH1 8Dh Time

150AT89C51314136A–USB–03/03ONCE Mode (ON Chip Emulation)The ONCE mode facilitates testing and debugging of systems using AT89C5131 withoutremoving the

151AT89C51314136A–USB–03/03Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used withexternal program or d

152AT89C51314136A–USB–03/03Electrical CharacteristicsAbsolute Maximum Ratings DC Parameters for Standard VoltageTA = -40°C to +85°C; VSS = 0V; VCC = 5

153AT89C51314136A–USB–03/03DC Parameters for Low VoltageTA = -40°C to +85°C; VSS = 0V; VCC = 3.3V ± 10%; F = 0 to 40 MHzNotes: 1. Operating ICC is mea

154AT89C51314136A–USB–03/036. Under steady state (non-transient) conditions, IOL must be externally limited as follows:Maximum IOL per port pin: 10 mA

155AT89C51314136A–USB–03/03Figure 68. ICC Test Condition, Power-down ModeFigure 69. Clock Signal Waveform for ICC Tests in Active and Idle ModesRSTE

156AT89C51314136A–USB–03/03USB DC ParametersSymbol Parameter Min Typ Max UnitVREFUSB Reference Voltage 3.0 3.6 VVIHInput High Voltage for D+ and D- (D

157AT89C51314136A–USB–03/03AC ParametersExplanation of the AC SymbolsEach timing symbol has 5 characters. The first character is always a “T” (stands

158AT89C51314136A–USB–03/03Table 105. AC Parameters for a Fix Clock (F = 40 MHz)Table 106. AC Parameters for a Variable ClockSymbol Min Max UnitsT25

159AT89C51314136A–USB–03/03External Program Memory Read CycleExternal Data Memory CharacteristicsTable 107. Symbol DescriptionTPLIVTPLAZALEPSENPORT 0

16AT89C51314136A–USB–03/03Table 18. PCA SFR’sMnemo-nic Add Name 7 6 5 4 3 2 1 0CCON D8h PCA Timer/Counter Control CF CR CCF4 CCF3 CCF2 CCF1 CCF0CMOD

160AT89C51314136A–USB–03/03Table 108. AC Parameters for a Variable Clock (F = 40 MHz)Symbol Min Max UnitsTRLRH130 nsTWLWH130 nsTRLDV100 nsTRHDX0nsTRH

161AT89C51314136A–USB–03/03Table 109. AC Parameters for a Variable ClockExternal Data Memory Write CycleSymbol TypeStandard Clock X2 Clock X Paramete

162AT89C51314136A–USB–03/03External Data Memory Read CycleSerial Port Timing - Shift Register ModeTable 110. Symbol Description (F = 40 MHz)Table 111

163AT89C51314136A–USB–03/03Shift Register Timing WaveformExternal Clock Drive Characteristics (XTAL1)Table 113. AC ParametersExternal Clock Drive Wav

164AT89C51314136A–USB–03/03Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.This diagram indicates when signals

165AT89C51314136A–USB–03/03Flash Memory Table 114. Timing Symbol DefinitionsTable 115. Memory AC TimingVDD = 5V ± 10%, TA = -40 to +85°CFigure 70.

166AT89C51314136A–USB–03/03USB AC ParametersRise Time Fall TimeVCRSDifferentialData Lines90%10%90%10%tRtFVHminVLmaxTable 116. USB AC Parameters Symbo

167AT89C51314136A–USB–03/03Ordering InformationNote: 1. Optional Packing and Package options (please consult Atmel sales representative):-Tape and Ree

168AT89C51314136A–USB–03/03Packaging Information64-lead VQFP

169AT89C51314136A–USB–03/0352-lead PLCC

17AT89C51314136A–USB–03/03Table 21. Keyboard SFRsMnemonicAddName 76543210KBF 9EhKeyboard Flag RegisterKBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0KBE 9DhK

170AT89C51314136A–USB–03/0348-lead MLF

171AT89C51314136A–USB–03/0328-lead SO

i AT89C51314136A–USB–03/03Table of ContentsFeatures ...

ii AT89C51314136A–USB–03/03In-System Programming (ISP) ... 53Flash Programming and Erasure...

iii AT89C51314136A–USB–03/03Introduction... 113De

Printed on recycled paper.© Atmel Corporation 2003. All rights reserved. Atmel, the Atmel logo, and combinations thereof are registeredtrademarks of

18AT89C51314136A–USB–03/03Table 24. Other SFR’sMnemonicAddName 76543210PCON 87h Power Control SMOD1 SMOD0 - POF GF1 GF0 PD IDLAUXR 8Eh Auxiliary Regi

19AT89C51314136A–USB–03/03Clock ControllerIntroduction The AT89C5131 clock controller is based on an on-chip oscillator feeding an on-chipPhase Lock L

2AT89C51314136A–USB–03/03Description AT89C5131 is a high-performance Flash version of the 80C51 single-chip 8-bit micro-controllers with full speed US

20AT89C51314136A–USB–03/03Figure 6. Crystal ConnectionPLLPLL Description The AT89C5131 PLL is used to generate internal high frequency clock (the USB

21AT89C51314136A–USB–03/03PLL Programming The PLL is programmed using the flow shown in Figure 9. As soon as clock generationis enabled user must wait

22AT89C51314136A–USB–03/03Registers Table 26. CKCON0 (S:8Fh)Clock Control Register 0Reset Value = 0000 0000b76543210- WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2

23AT89C51314136A–USB–03/03Table 27. CKCON1 (S:AFh)Clock Control Register 1Reset Value = 0000 0000bTable 28. PLLCON (S:A3h)PLL Control RegisterReset

24AT89C51314136A–USB–03/03Dual Data Pointer RegisterThe additional data pointer can be used to speed up code execution and reduce codesize.The dual DP

25AT89C51314136A–USB–03/03ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of ent

26AT89C51314136A–USB–03/03Program/Code MemoryThe AT89C5131 implement 32 Kbytes of on-chip program/code memory. Figure 11shows the split of internal an

27AT89C51314136A–USB–03/03Table 31. External Data Memory Interface SignalsExternal Bus Cycles This section describes the bus cycles the AT89C5131 exe

28AT89C51314136A–USB–03/03Figure 14. Flash Memory ArchitectureFM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 14):1. The

29AT89C51314136A–USB–03/03The other memory spaces (user, extra row, hardware security) are made accessible inthe code segment by programming bits FMOD

3AT89C51314136A–USB–03/03Block DiagramNotes: 1. Alternate function of Port 12. Alternate function of Port 33. Alternate function of Port 4 (Alternate

30AT89C51314136A–USB–03/03Loading the Column Latches Any number of data from 1 byte to 128 bytes can be loaded in the column latches. Thisprovides the

31AT89C51314136A–USB–03/03Extra Row The following procedure is used to program the Extra Row space and is summarized inFigure 16:• Load data in the co

32AT89C51314136A–USB–03/03Hardware Security The following procedure is used to program the Hardware Security space and is sum-marized in Figure 17:• S

33AT89C51314136A–USB–03/03Reading the Flash SpacesUser The following procedure is used to read the User space and is summarized in Figure 18:• Map the

34AT89C51314136A–USB–03/03Registers Table 34. FCON (S:D1h)Flash Control RegisterReset Value = 0000 0000b76543210FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 F

35AT89C51314136A–USB–03/03Flash EEPROM MemoryGeneral Description The Flash memory increases EPROM functionality with in-circuit electrical erasure and

36AT89C51314136A–USB–03/03Flash Registers and Memory MapThe AT89C5131 Flash memory uses several registers:• Hardware registers can only be accessed th

37AT89C51314136A–USB–03/03Table 36. Program Lock bitsNotes: 1. U: unprogrammed or “one” level.2. P: programmed or “zero” level.3. X: don’t care4. WAR

38AT89C51314136A–USB–03/03Table 37. Software RegistersAfter programming the part by ISP, the BSB must be cleared (00h) in order to allow theapplicati

39AT89C51314136A–USB–03/03The two lock bits provide different levels of protection for the on-chip code and data,when programmed as shown to Table 39.

4AT89C51314136A–USB–03/03Pinout DescriptionPinoutFigure 1. AT89C5131 52-pin PLCC Pinout21 22 26252423 292827 30 31 5 4 3 2 1 6 52 51 50 49 4

40AT89C51314136A–USB–03/03Boot ProcessBoot Flash When the user application programs its own Flash memory, all of the low level detailsare handled by a

41AT89C51314136A–USB–03/03Figure 21. Boot Process FlowchartBLJB = 1?SBV < 3Fh?ATMEL BOOTLOADERAPPLICATION PROGRAMCUSTOMER BOOTLOADERPC = [SBV]00hY

42AT89C51314136A–USB–03/03In-System Programming (ISP)The In-System Programming (ISP) is performed without removing the microcontrollerfrom the system.

43AT89C51314136A–USB–03/03Table 40. Intel-Hex Records Used by In-System Programming Record Type Command/Data Function00Data Record:nnaaaa00dd...ddc

44AT89C51314136A–USB–03/0303Miscellaneous Write Functions:nnxxxx03ffssddccWhere:nn = number of bytes (hex) in recordxxxx = required field, but value i

45AT89C51314136A–USB–03/03In-application Programming MethodSeveral Application Program Interface (API) calls are available for use by an applicationpr

46AT89C51314136A–USB–03/03Table 41. API Calls API Call ParameterPROGRAM DATA BYTE Input Parameters:R0 = osc freq (integer Not required, left for Phi

47AT89C51314136A–USB–03/03PROGRAM SOFTWARE SECURITY BIT Input Parameters:R0 = osc freq (integer Not required, left for Philips compatibility)R1 = 05hD

48AT89C51314136A–USB–03/03PROGRAM OSC MODE Input Parameters:R0 = osc freq (integer Not required, left for Philips compatibility)R1 = 06hDPH = 00hDPL =

49AT89C51314136A–USB–03/03READ copy of the MANUFACTURER ID Input Parameters:R0 = osc freq (integer Not required, left for Philips compatibility)R1 = 0

5AT89C51314136A–USB–03/03Figure 2. AT89C5131 64-pin VQFP Pinout17 18 22212019 252423 26 27 62 61 60 59 58 63 57 56 55 54 5312 3 4 56 78 9 10 1

50AT89C51314136A–USB–03/03Note: 1. These functions can only be called by user’s code. The standard bootloader cannotdecrease the security level.READ B

51AT89C51314136A–USB–03/03EEPROM Data MemoryDescription The 1-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 03FFh ofthe XRAM memo

52AT89C51314136A–USB–03/03RegistersReset Value = XXXX XX00bNot bit addressableTable 42. EECON (S:0D2h)EECON Register76543210EEPL3 EEPL2 EEPL1 EEPL0 -

53AT89C51314136A–USB–03/03In-System Programming (ISP)With the implementation of the User EEPROM and the Boot EEPROM in Flash technol-ogy the AT89C5131

54AT89C51314136A–USB–03/03Flash Programming and ErasureThere are three methods of programming the Flash memory:• The Atmel bootloader located in FM1 i

55AT89C51314136A–USB–03/03WARNING: Security level 2 and 3 should only be programmed after Flash and Coreverification.Program Lock Bits These security

56AT89C51314136A–USB–03/03Figure 23. Low Pin-count Boot Process AlgorithmHigh Pin-Count Boot ProcessAt the falling edge of RESET, the bit ENBOOT in A

57AT89C51314136A–USB–03/03• ALE high (or not connected)– After Hardware Condition the FCON register is initialized with the value 00h and the PC is in

58AT89C51314136A–USB–03/03Application Programming InterfaceSeveral Application Program Interface (API) calls are available for use by an applicationpr

59AT89C51314136A–USB–03/03XROW Bytes Table 44. XRow MappingNotes: 1. Default value after erasing chip: FFh2. Only accessed by the API or in the paral

6AT89C51314136A–USB–03/03Figure 3. AT89C5131 48-pin MLF PinoutFigure 4. AT89C5131 28-pin SO Pinout13 14 18171615 212019 22 2346 45 44 43 42 47

60AT89C51314136A–USB–03/03Hardware ByteDefault value after erasing chip: FFhNotes: 1. Only the 4 MSB bits can be access by software.2. The 4 LSB bits

61AT89C51314136A–USB–03/03On-chip Expanded RAM (XRAM)The AT89C5131 provides additional Bytes of random access memory (RAM) space forincreased data par

62AT89C51314136A–USB–03/03When an instruction accesses an internal location above address 7Fh, the CPU knowswhether the access is to the upper 128 byt

63AT89C51314136A–USB–03/03Reset Value = 0X0X 1100bNot bit addressableTable 49. AUXR RegisterAUXR - Auxiliary Register (8Eh)76543210DPU - M0 - XRS1 XR

64AT89C51314136A–USB–03/03Timer 2 The Timer 2 in the AT89C5131 is the standard C52 Timer 2. It is a 16-bit timer/counter:the count is maintained by tw

65AT89C51314136A–USB–03/03Figure 26. Auto-reload Mode Up/Down Counter (DCEN = 1)Programmable Clock OutputIn the Clock-out mode, Timer 2 operates as a

66AT89C51314136A–USB–03/03It is possible to use Timer 2 as a baud rate generator and a clock generator simulta-neously. For this configuration, the ba

67AT89C51314136A–USB–03/03Reset Value = 0000 0000bBit addressableTable 50. T2CON RegisterT2CON - Timer 2 Control Register (C8h)76543210TF2 EXF2 RCLK

68AT89C51314136A–USB–03/03Reset Value = XXXX XX00bNot bit addressableTable 51. T2MOD RegisterT2MOD - Timer 2 Mode Control Register (C9h)76543210-----

69AT89C51314136A–USB–03/03Programmable Counter Array (PCA)The PCA provides more timing capabilities with less CPU intervention than the standardtimer/

7AT89C51314136A–USB–03/03Signals All the AT89C5131 signals are detailed by functionality on Table 1 through Table 11.Table 1. Keypad Interface Signal

70AT89C51314136A–USB–03/03Figure 28. PCA Timer/CounterTable 52. CMOD RegisterCMOD - PCA Counter Mode Register (D9h)Reset Value = 00XX X000bNot bit a

71AT89C51314136A–USB–03/03The CMOD register includes three additional bits associated with the PCA (SeeFigure 28 and Table 52).• The CIDL bit allows t

72AT89C51314136A–USB–03/03The watchdog timer function is implemented in module 4 (See Figure 31). The PCA interrupt system is shown in Figure 29.Figur

73AT89C51314136A–USB–03/03the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either

74AT89C51314136A–USB–03/03Table 55. PCA Module Modes (CCAPMn Registers)There are two additional registers associated with each of the PCA modules. Th

75AT89C51314136A–USB–03/03Table 56. CCAPnH Registers (n = 0-4)CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)CCAP1H - PCA Module 1

76AT89C51314136A–USB–03/03Table 59. CL RegisterCL - PCA Counter Register Low (0E9h)Reset Value = 0000 0000bNot bit addressablePCA Capture Mode To use

77AT89C51314136A–USB–03/03Figure 31. PCA Compare Mode and PCA Watchdog TimerNote: 1. Only for Module 4Before enabling ECOM bit, CCAPnL and CCAPnH sho

78AT89C51314136A–USB–03/03Figure 32. PCA High-speed Output ModeBefore enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,otherw

79AT89C51314136A–USB–03/03Figure 33. PCA PWM ModePCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability

8AT89C51314136A–USB–03/03Table 5. LED Signal DescriptionTable 6. SPI Signal DescriptionT0 ITimer Counter 0 External Clock InputWhen Timer 0 operates

80AT89C51314136A–USB–03/03Serial I/O Port The serial I/O port in the AT89C5131 is compatible with the serial I/O port in the 80C52.It provides both sy

81AT89C51314136A–USB–03/03Figure 36. UART Timings in Modes 2 and 3Automatic Address RecognitionThe automatic address recognition feature is enabled w

82AT89C51314136A–USB–03/03The SADEN byte is selected so that each slave may be addressed separately.For slave A, bit 0 (the LSB) is a don’t care bit;

83AT89C51314136A–USB–03/03SADDR - Slave Address Register (A9h)Reset Value = 0000 0000bNot bit addressableBaud Rate Selection for UART for Mode 1 and 3

84AT89C51314136A–USB–03/03Figure 38. Internal Baud Rate• The baud rate for UART is token by formula: BRG01/6BRL/201INT_BRGSPDBRRSMOD1auto reload coun

85AT89C51314136A–USB–03/03Table 60. SCON Register – SCON Serial Control Register (98h)Reset Value = 0000 0000bBit addressable76543210FE/SM0 SM1 SM2 R

86AT89C51314136A–USB–03/03Example of computed value when X2 = 1, SMOD1 = 1, SPD = 1Example of computed value when X2 = 0, SMOD1 = 0, SPD = 0The baud r

87AT89C51314136A–USB–03/03BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)Reset Value = 0000 0000bTable 61. T2CON Reg

88AT89C51314136A–USB–03/03Table 62. PCON RegisterPCON - Power Control Register (87h)Reset Value = 00X1 0000bNot bit addressablePower-off flag reset v

89AT89C51314136A–USB–03/03Table 63. BDRCON RegisterBDRCON - Baud Rate Control Register (9Bh)Reset Value = XXX0 0000bNot bit addressable7 6 5 4 3 2 1

9AT89C51314136A–USB–03/03Table 7. Ports Signal DescriptionTable 8. Clock Signal DescriptionTable 9. USB Signal DescriptionSignal Name Type Descript

90AT89C51314136A–USB–03/03Interrupt SystemOverview The AT89C5131 has a total of 15 interrupt vectors: two external interrupts (INT0 andINT1), three ti

91AT89C51314136A–USB–03/03Each of the interrupt sources can be individually enabled or disabled by setting or clear-ing a bit in the Interrupt Enable

92AT89C51314136A–USB–03/03Table 65. IE0 RegisterIE0 - Interrupt Enable Register (A8h)Reset Value = 0000 0000bBit addressable7 6 5 4 3 2 1 0EA EC ET2

93AT89C51314136A–USB–03/03Table 66. IPL0 RegisterIPL0 - Interrupt Priority Register (B8h)Reset Value = X000 0000bBit addressable7 6 5 4 3 2 1 0- PPCL

94AT89C51314136A–USB–03/03Table 67. IPH0 RegisterIPH0 - Interrupt Priority High Register (B7h)Reset Value = X000 0000bNot bit addressable7 6 5 4 3 2

95AT89C51314136A–USB–03/03Table 68. IE1 RegisterIE1 - Interrupt Enable Register (B1h)Reset Value = XXXX X000bBit addressable7 6 5 4 3 2 1 0- EUSB - -

96AT89C51314136A–USB–03/03Table 69. IPL1 RegisterIPL1 - Interrupt Priority Register (B2h)Reset Value = XXXX X000bBit addressable7 6 5 4 3 2 1 0- PUSB

97AT89C51314136A–USB–03/03Table 70. IPH1 RegisterIPH1 - Interrupt Priority High Register (B3h)Reset Value = XXXX X000bNot bit addressable7 6 5 4 3 2

98AT89C51314136A–USB–03/03Interrupt Sources and Vector AddressesTable 71. Vector TableNumberPolling PriorityInterrupt SourceInterruptRequestVector Ad

99AT89C51314136A–USB–03/03Keyboard InterfaceIntroduction The AT89C5131 implements a keyboard interface allowing the connection of a 8 x nmatrix keyboa