Rainbow-electronics ATmega128L Manual de usuario descargar pdf (Pagina 132)

132

ATmega128(L)

2467B–09/01

Timer/Counter 3 Control

• Bit 7- FOCnA: Force Output Compare for Channel A

• Bit 6- FOCnB: Force Output Compare for Channel B

• Bit 5- FOCnC: Force Output Compare for Channel C

The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a

non-PWM mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an

immediate compare match is forced on the waveform generation unit. The

OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that

the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value

present in the COMnx1:0 bits that determine the effect of the forced compare.

A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer

in clear timer on compare match (CTC) mode using OCRnA as TOP.

The FOCnA/FOCnB/FOCnB bits are always read as zero.

• Bit 4:0 - Reserved Bits

These bits are reserved for future use. For ensuring compatibility with future devices,

these bits must be written to zero when TCCRnC is written.

Timer/Counter 1 – TCNT1H

and TCNT1L

Timer/Counter 3 – TCNT3H

and TCNT3L

The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give

direct access, both for read and for write operations, to the Timer/Counter unit 16-bit

counter. To ensure that both the high and low bytes are read and written simultaneously

when the CPU accesses these registers, the access is performed using an 8-bit tempo-

rary high byte register (TEMP). This temporary register is shared by all the other 16-bit

registers.

See “Accessing 16-bit Registers” on page 109.

Modifying the counter (TCNTn) while the counter is running introduces a risk of missing

a compare match between TCNTn and one of the OCRnx registers.

Writing to the TCNTn register blocks (removes) the compare match on the following

timer clock for all compare units.

Bit 76543210

FOC3A FOC3B FOC3C –––––TCCR3C

Read/Write W W W R R R R R

Initial value00000000

Bit 76543210

TCNT1[15:8] TCNT1H

TCNT1[7:0] TCNT1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

TCNT3[15:8] TCNT3H

TCNT3[7:0] TCNT3L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

1 2 ... 127 128 129 130 131 132 133 134 135 136 137 ... 330 331

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