
225
ATmega128(L)
2467B–09/01
Figure 109. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 110. ADC Timing Diagram, Single Conversion
Figure 111. ADC Timing Diagram, Free Running Conversion
Sign and MSB of result
LSB of result
ADC clock
ADSC
Sample & hold
ADIF
ADCH
ADCL
Cycle number
ADEN
1 212
13
14 15
16 17
18
19 20 21 22 23
24 25
1 2
First Conversion
Next
Conversion
3
MUX and REFS
update
MUX and REFS
update
Conversion
complete
1
2 3 4 5 6 7 8
9
10 11 12 13
Sign and MSB of result
LSB of result
ADC clock
ADSC
ADIF
ADCH
ADCL
Cycle number
12
One Conversion Next Conversion
3
Sample & hold
MUX and REFS
update
Conversion
complete
MUX and REFS
update
11 12 13
Sign and MSB of result
LSB of result
ADC clock
ADSC
ADIF
ADCH
ADCL
Cycle number
12
One Conversion Next Conversion
34
Conversion
complete
Sample & hold
MUX and REFS
update
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