Rainbow-electronics ATmega32L Manual de usuario descargar pdf (Pagina 32)

ATmega32(L)

2503C–AVR–10/02

Asynchronous Timer should be considered undefined after wake-up in Power-save

mode if AS2 is 0.

This sleep mode basically halts all clocks except clk

ASY

, allowing operation only of asyn-

chronous modules, including Timer/Counter2 if clocked asynchronously.

Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,

the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to

Power-down with the exception that the Oscillator is kept running. From Standby mode,

the device wakes up in six clock cycles.

Extended Standby Mode When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected,

the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is

identical to Power-save mode with the exception that the Oscillator is kept running.

From Extended Standby mode, the device wakes up in six clock cycles..

Notes: 1. External Crystal or resonator selected as clock source.

2. If AS

2 bit in ASSR is set.

3. Only INT2 or level interrupt INT1 and INT0.

Minimizing Power

Consumption

There are several issues to consider when trying to minimize the power consumption in

an AVR controlled system. In general, sleep modes should be used as much as possi-

ble, and the sleep mode should be selected so that as few as possible of the device’s

functions are operating. All functions not needed should be disabled. In particular, the

following modules may need special consideration when trying to achieve the lowest

possible power consumption.

Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should

be disabled before entering any sleep mode. When the ADC is turned off and on again,

the next conversion will be an extended conversion. Refer to “Analog to Digital Con-

verter” on page 199 for details on ADC operation.

Table 14. Active Clock Domains and Wake Up Sources in the Different Sleep Modes

Active Clock domains Oscillators Wake-up Sources

Sleep Mode

clk

CPU

clk

FLASH

clk

ADC

clk

ASY

Main Clock

Source Enabled

Timer Oscillator

Enabled

INT2

INT1

INT0

TWI Address

Match

Timer

SPM / EEPROM

Ready

ADC

Other

I/O

Idle X X X X X

(2)

X XXXXX

ADC Noise

Reduction

XX X X

(2)

(3)

XXXX

Power-down X

(3)

Power-save X

(2)

(3)

(2)

Standby

(1)

(3)

Extended

Standby

(1)

(2)

(3)

(2)

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 312 313

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