Rainbow-electronics ATmega32L Manual de usuario descargar pdf (Pagina 230)

230

ATmega32(L)

2503C–AVR–10/02

Figure 120. Boundary-scan Cells for Oscillators and Clock Options

Table 90 summaries the scan registers for the external clock pin XTAL1, Oscillators with

XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.

Notes: 1. Do not enable more than one clock source as main clock at a time.

2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift

between the Internal Oscillator and the JTAG TCK clock. If possible, scanning an

external clock is preferred.

3. The clock configuration is programmed by fuses. As a fuse is not changed run-time,

the clock configuration is considered fixed for a given application. The user is advised

to scan the same clock option as to be used in the final system. The enable signals

are supported in the scan chain because the system logic can disable clock options

in sleep modes, thereby disconnecting the Oscillator pins from the scan path if not

provided. The INTCAP fuses are not supported in the scan-chain, so the boundary

scan chain can not make a XTAL Oscillator requiring internal capacitors to run unless

the fuse is correctly programmed.

Scanning the Analog

Comparator

The relevant Comparator signals regarding Boundary-scan are shown in Figure 121.

The Boundary-scan cell from Figure 122 is attached to each of these signals. The sig-

nals are described in Table 91.

The Comparator need not be used for pure connectivity testing, since all analog inputs

are shared with a digital port pin as well.

Table 90. Scan Signals for the Oscillator

(1)(2)(3)

Enable Signal Scanned Clock Line Clock Option

Scanned Clock Line

when not Used

EXTCLKEN EXTCLK (XTAL1) External Clock 0

OSCON OSCCK External Crystal

External Ceramic

Resonator

RCOSCEN RCCK External RC 0

OSC32EN OSC32CK Low Freq. External Crystal 1

TOSKON TOSCK 32 kHz Timer Oscillator 0

From

Cell

ClockDR

ShiftDR

Cell

To System Logic

FF1

DQ DQ

From

Cell

ClockDR UpdateDR

ShiftDR

Cell EXTEST

From Digital Logic

XTAL1/TOSC1 XTAL2/TOSC2

Oscillator

ENABLE OUTPUT

1 2 ... 225 226 227 228 229 230 231 232 233 234 235 ... 312 313

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