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177

ATmega32(L)

2503C–AVR–10/02

• Bits 1..0 – TWPS: TWI Prescaler Bits

These bits can be read and written, and control the bit rate prescaler.

To calculate bit rates, see “Bit Rate Generator Unit” on page 173. The value of

TWPS1..0 is used in the equation.

TWI Data Register – TWDR

In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the

TWDR contains the last byte received. It is writable while the TWI is not in the process of

shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware.

Note that the data register cannot be initialized by the user before the first interrupt

occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted

out, data on the bus is simultaneously shifted in. TWDR always contains the last byte

present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In

this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no

data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled

automatically by the TWI logic, the CPU cannot access the ACK bit directly.

• Bits 7..0 – TWD: TWI Data Register

These eight bits contin the next data byte to be transmitted, or the latest data byte

received on the Two-wire Serial Bus.

TWI (Slave) Address Register

– TWAR

The TWAR should be loaded with the 7-bit slave address (in the seven most significant

bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or

receiver. In multimaster systems, TWAR must be set in masters which can be

addressed as slaves by other masters.

The LSB of TWAR is used to enable recognition of the general call address ($00). There

is an associated address comparator that looks for the slave address (or general call

address if enabled) in the received serial address. If a match is found, an interrupt

request is generated.

• Bits 7..1 – TWA: TWI (Slave) Address Register

These seven bits constitute the slave address of the TWI unit.

Table 73. TWI Bit Rate Prescaler

TWPS1 TWPS0 Prescaler Value

001

014

1016

1164

Bit 76543210

TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 TWDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 1 1 1 1 1 1 1 1

Bit 76543210

TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 1 1 1 1 1 1 1 0

1 2 ... 172 173 174 175 176 177 178 179 180 181 182 ... 312 313

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