Rainbow-electronics ATmega32L Manual de usuario descargar pdf (Pagina 135)

135

ATmega32(L)

2503C–AVR–10/02

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written

logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will

be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to

re-enable SPI Master mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero,

SCK is low when idle. Refer to Figure 67 and Figure 68 for an example. The CPOL func-

tionality is summarized below:

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading

(first) or trailing (last) edge of SCK. Refer to Figure 67 and Figure 68 for an example.

The CPHA functionality is summarized below:

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and

SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator

Clock frequency f

osc

is shown in the following table:

Table 56. CPOL Functionality

CPOL Leading Edge Trailing Edge

0 Rising Falling

1 Falling Rising

Table 57. CPHA Functionality

CPHA Leading Edge Trailing Edge

0 Sample Setup

1Setup Sample

Table 58. Relationship Between SCK and the Oscillator Frequency

SPI2X SPR1 SPR0 SCK Frequency

000

osc

001

osc

/16

010

osc

/64

011

osc

/128

100

osc

101

osc

110

osc

/32

111

osc

/64

1 2 ... 130 131 132 133 134 135 136 137 138 139 140 ... 312 313

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