MAX1329/MAX1330
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
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The four conversion modes programmed by the
APD<1:0> and AUTO<2:0> bits in the ADC Control
register are: autoconvert, fast power-down, normal, and
burst modes. In normal and fast power-down modes,
single conversions are initiated with the ADC convert
command or by toggling a configured DPIO. In fast
power-down mode, the PGA and ADC power down
between conversions to reduce power. A minimum of
16 clock cycles is required to complete a conversion in
normal or fast power-down mode.
Burst mode is initiated with one ADC convert com-
mand and continuously converts on the same channel
sending the data directly to DOUT as long as there is
activity on SCLK and CS is low. Burst mode aborts
when CS goes high. In burst mode, SCLK directly
clocks the ADC. For best performance, synchronize
SCLK with the CLKIO clock (see Figure 18). A mini-
mum of 14 clock cycles is required to complete a con-
version in burst mode.
X = DON'T CARE.
X = DON'T CARE.
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