MAX1329/MAX1330
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________ 11
TIMING CHARACTERISTICS (continued)
(DV
DD
= 1.8V to 3.6V, AV
DD
= 2.7V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK to APIO3 Propagation
Delay
t
DSA
AP3MD<1:0> = 11, CS is high 30 ns
DIN to APIO2 Propagation Delay
t
DDA
AP2MD<1:0> = 11, CS is high 25 ns
APIO1 to DOUT Propagation
Delay
t
DAD
AP1MD<1:0> = 11, CS is high 20 ns
SPI-Mode Propagation Delay
Matching
t
DM
Among APIO4, APIO3, APIO2, and APIO1 ±10 ns
ANALOG PROGRAMMABLE I/O TIMING PARAMETERS (APIO1–APIO4, DV
DD
= 1.8V to 3.6V, AV
DD
= 2.7V to 5.5V, C
L
= 20pF)
SPI Write to APIO Output Valid
t
SD
From last SCLK rising edge 100 ns
APIO Rise/Fall Input to Interrupt
Asserted Delay
t
DI
Interrupt programmed on RST1 and/or
RST2, corresponding status bits unmasked
175 ns
CS to APIO4 Propagation Delay
t
DCA
AP4MD<1:0> = 11 60 ns
SCLK to APIO3 Propagation
Delay
t
DSA
AP3MD<1:0> = 11, CS is high 50 ns
DIN to APIO2 Propagation Delay
t
DDA
AP2MD<1:0> = 11, CS is high 50 ns
APIO1 to DOUT Propagation
Delay
t
DAD
AP1MD<1:0> = 11, CS is high 80 ns
SPI-Mode Propagation Delay
Matching
t
DM
Among APIO4, APIO3, APIO2, and APIO1 ±30 ns
Note 1: ADC INL and DNL, offset, and gain are tested at DV
DD
= 1.8V, AV
DD
= 2.7V, f
SAMPLE
= 234ksps to guarantee performance
at f
SAMPLE
= 312ksps, DV
DD
≥ 2.7V and AV
DD
≥ 5.0V.
Note 2: Guaranteed by design. Not production tested.
Note 3: AV
DD
supply current contribution for this module.
Note 4: DNL and INL are measured between code 115 and 4095.
Note 5: Temperature sensor accuracy is tested using a 2.5084V reference applied to REFADJ.
Note 6: The maximum trip levels for the AV
DD
monitor are 5% below the typical charge-pump output value. The charge-pump output
voltage and the trip thresholds track to prevent tripping at -5% below the typical charge-pump output value.
Note 7: DV
DD
supply current contribution for this module.
Note 8: The normal operation and sleep mode supply currents are measured with no load on DOUT, SCLK idle, and all digital inputs
at DGND or DV
DD
. CLKIO runs in normal mode operation and idle in sleep mode.
(27 paginas)
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