Rev.A - May 17, 2001 7
Preliminary
T89C51CC02
4.3. Read-Modify-Write Instructions
Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify
the data and then rewrite the latch. These are called "Read-Modifiy-Write" instructions. Below is a complete list
of these special instructions (see Table 2). When the destination operand is a Port or a Port bit, these instructions
read the latch rather than the pin:
Table 2. Read-Modify-Write Instructions
It is not obvious the last three instructions in this list are Read-Modify-Write instructions. These instructions read
the port (all 8 bits), modify the specifically addressed bit and write the new byte back to the latch. These Read-
Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation
of voltage (and therefore, logic)levels at the pin. For example, a Port bit used to drive the base of an external
bipolar transistor can not rise above the transistor’s base-emitter junction voltage (a value lower than VIL). With
a logic one written to the bit, attemps by the CPU to read the Port at the pin are misinterpreted as logic zero. A
read of the latch rather than the pins returns the correct logic-one value.
4.4. Quasi-Bidirectional Port Operation
Port 1, Port 3 and Port 4 have fixed internal pull-ups and are referred to as "quasi-bidirectional" Ports. When
configured as an input, the pin impedance appears as logic one and sources current in response to an external logic
zero condition. Resets write logic one to all Port latches. If logical zero is subsequently written to a Port latch, it
can be returned to input condions by a logical one written to the latch.
NOTE:
Port latch values change near the end of Read-Modify-Write insruction cycles. Output buffers (and therefore the pin state) update early in the
instruction after Read-Modify-Write instruction cycle.
Logical zero-to-one transitions in Port 1, Port 3 and Port 4 use an additional pull-up (p1) to aid this logic transition
see Figure. This increases switch speed. This extra pull-up sources 100 times normal internal circuit current during
2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups
consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logical zero and off when the
gate senses logical one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition
in the Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This
inverter and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched on whenever
the associated nFET is switched off. This is traditional CMOS switch convention. Current strengths are 1/10 that
of pFET #3.
Instruction Description Example
ANL logical AND ANL P1, A
ORL logical OR ORL P2, A
XRL logical EX-OR XRL P3, A
JBC jump if bit = 1 and clear bit JBC P1.1, LABEL
CPL complement bit CPL P3.0
INC increment INC P2
DEC decrement DEC P2
DJNZ decrement and jump if not zero DJNZ P3, LABEL
MOV Px.y, C move carry bit to bit y of Port x MOV P1.5, C
CLR Px.y clear bit y of Port x CLR P2.4
SET Px.y set bit y of Port x SET P3.3
(33 paginas)
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