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ATtiny11/12

1006C–09/01

• Bit 3 - ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana-

log Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled.

• Bit 2 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny11/12 and will always read as zero.

• Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator Inter-

rupt. The different settings are shown in Table 18.

Note: When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-

abled by clearing its interrupt enable bit in the ACSR register. Otherwise, an interrupt can

occur when the bits are changed.

Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write

a one back into ACI if it is read as set, thus clearing the flag.

Table 18. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle

01Reserved

1 0 Comparator Interrupt on Falling Output Edge

1 1 Comparator Interrupt on Rising Output Edge

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 85 86

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Rainbow-electronics ATtiny12 Manual de usuario Pagina 40