Rainbow-electronics ATtiny12 Manual de usuario Pagina 1

1Features• Utilizes the AVR® RISC Architecture• High-performance and Low-power 8-bit RISC Architecture– 90 Powerful Instructions – Most Single Clock C

10ATtiny11/121006C–09/01OR and all other operations between two registers or on a single register apply to theentire register file.Registers 30 and 31

11ATtiny11/121006C–09/01Register Indirect Figure 9. Indirect Register AddressingThe register accessed is the one pointed to by the Z-register (R31, R

12ATtiny11/121006C–09/01Relative Program Addressing, RJMP and RCALLFigure 12. Relative Program Memory AddressingProgram execution continues at addres

13ATtiny11/121006C–09/01EEPROM Data Memory The ATtiny12 contains 64 bytes of data EEPROM memory. It is organized as a separatedata space, in which sin

14ATtiny11/121006C–09/01I/O Memory The I/O space definition of the ATtiny11/12 is shown in the following table:Note: Reserved and unused locations are

15ATtiny11/121006C–09/01pendent of the individual interrupt enable settings. The I-bit is cleared by hardware afteran interrupt has occurred, and is s

16ATtiny11/121006C–09/01The most typical and general program setup for the reset and interrupt vector addressesfor the ATtiny11 are:Address Labels Cod

17ATtiny11/121006C–09/01Reset Sources The ATtiny11/12 provides three or four sources of reset:• Power-on Reset. The MCU is reset when the supply volta

18ATtiny11/121006C–09/01Power-on Reset for the ATtiny11A Power-on Reset (POR) circuit ensures that the device is reset from power-on. Asshown in Figur

19ATtiny11/121006C–09/01Figure 17. Reset Logic for the ATtiny12Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPO

2ATtiny11/121006C–09/01Description The ATtiny11/12 is a low-power CMOS 8-bit microcontroller based on the AVR RISCarchitecture. By executing powerful

20ATtiny11/121006C–09/01Note: 1. Due to the limited number of clock cycles in the start-up period, it is recommendedthat Ceramic Resonator be used.Thi

21ATtiny11/121006C–09/01Power-on Reset for the ATtiny12A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec-tion level

22ATtiny11/121006C–09/01Figure 20. External Reset during OperationBrown-out Detection (ATtiny12)ATtiny12 has an on-chip brown-out detection (BOD) cir

23ATtiny11/121006C–09/01Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle dura-tion. On the falling edge

24ATtiny11/121006C–09/01MCU Status Register – MCUSR for the ATtiny12The MCU Status Register provides information on which reset source caused an MCUre

25ATtiny11/121006C–09/01bandgap reference uses approximately 10 µA, and to reduce power consumption inPower-down mode, the user can turn off the refer

26ATtiny11/121006C–09/01interrupt is activated on rising or falling edge, on pin change, or low level of the INT0 pin.Activity on the pin will cause a

27ATtiny11/121006C–09/01• Bit 0 - Res: Reserved BitThis bit is a reserved bit in the ATtiny11/12 and always reads as zero.Timer/Counter Interrupt Flag

28ATtiny11/121006C–09/01MCU Control Register – MCUCRThe MCU Control Register contains control bits for general MCU functions.Note: The Pull-up Disable

29ATtiny11/121006C–09/01Sleep Modes for the ATtiny11To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-tion must be e

3ATtiny11/121006C–09/01Figure 1. The ATtiny11 Block DiagramPROGRAMCOUNTERINTERNALOSCILLATORWATCHDOGTIMERSTACKPOINTERPROGRAMFLASHHARDWARESTACKMCU CONT

30ATtiny11/121006C–09/01Note that if a level triggered or pin change interrupt is used for wake-up from Power-down Mode, the changed level must be hel

31ATtiny11/121006C–09/01Timer/Counter0 The ATtiny11/12 provides one general-purpose 8-bit Timer/Counter – Timer/Counter0.The Timer/Counter0 has presca

32ATtiny11/121006C–09/01Figure 24. Timer/Counter0 Block DiagramTimer/Counter0 Control Register – TCCR0• Bits 7..3 - Res: Reserved BitsThese bits are

33ATtiny11/121006C–09/01The Stop condition provides a Timer Enable/Disable function. The CK down-dividedmodes are scaled directly from the CK oscillat

34ATtiny11/121006C–09/01Watchdog Timer The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling theWatchdog Timer prescaler, t

35ATtiny11/121006C–09/011. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to

36ATtiny11/121006C–09/01ATtiny12 EEPROM Read/Write AccessThe EEPROM access registers are accessible in the I/O space.The write access time is in the r

37ATtiny11/121006C–09/01selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWEhas been set (one) by software, hardware clear

38ATtiny11/121006C–09/01Prevent EEPROM CorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply volt-age is too low fo

39ATtiny11/121006C–09/01Analog Comparator The Analog Comparator compares the input values on the positive input PB0 (AIN0) andnegative input PB1 (AIN1

4ATtiny11/121006C–09/01ATtiny12 Block Diagram Figure 2. The ATtiny12 Block DiagramThe ATtiny12 provides the following features: 1K bytes of Flash, 64

40ATtiny11/121006C–09/01• Bit 3 - ACIE: Analog Comparator Interrupt EnableWhen the ACIE bit is set (one) and the I-bit in the Status Register is set (

41ATtiny11/121006C–09/01I/O Port B All AVR ports have true read-modify-write functionality when used as general digital I/Oports. This means that the

42ATtiny11/121006C–09/01Port B Data Register – PORTBPort B Data Direction Register – DDRBNote: DDB5 is only available in ATtiny12.Port B Input Pins Ad

43ATtiny11/121006C–09/01Alternate Functions of Port B All port B pins are connected to a pin change detector that can trigger the pin changeinterrupt.

44ATtiny11/121006C–09/01Memory ProgrammingProgram (and Data) Memory Lock BitsThe ATtiny11/12 MCU provides two lock bits which can be left unprogrammed

45ATtiny11/121006C–09/01• CKSEL3..0 fuses: See Table 3, “Device Clocking Options Select,” on page 5 and Ta bl e 9 , “ATtiny12 Clock Options and Start

46ATtiny11/121006C–09/01provides a convenient way to download program and data into the ATtiny12 inside theuser’s system.The program and data memory a

47ATtiny11/121006C–09/01High-voltage Serial Programming AlgorithmTo program and verify the ATtiny11/12 in the High-voltage Serial Programming mode,the

48ATtiny11/121006C–09/01Figure 28. High-voltage Serial Programming WaveformsMSBMSBMSB LSBLSBLSB012345678910SERIAL DATA INPUTPB0SERIAL INSTR. INPUTPB1

49ATtiny11/121006C–09/01Note: a = address high bitsb = address low bitsi = data ino = data outx = don’t care1 = Lock Bit12 = Lock Bit23 = CKSEL0 Fuse4

5ATtiny11/121006C–09/01The ATtiny12 AVR is supported with a full suite of program and system developmenttools including: macro assemblers, program deb

50ATtiny11/121006C–09/01High-voltage Serial Programming CharacteristicsFigure 29. High-voltage Serial Programming TimingLow-voltage Serial Downloadin

51ATtiny11/121006C–09/01If the chip Erase command in Low-voltage Serial Programming is executed only once,one data byte may be written to the flash af

52ATtiny11/121006C–09/01next instruction. See Table 28 on page 54 for tWD_FLASH and tWD_EEPROM values. In an erased device, no $FFs in the data file(s

53ATtiny11/121006C–09/01Note: a = address high bitsb = address low bitsH = 0 - Low byte, 1 - High byteo = data outi = data inx = don’t care1 = Lock bi

54ATtiny11/121006C–09/01Low-voltage Serial Programming CharacteristicsFigure 32. Low-voltage Serial Programming TimingTable 26. Low-voltage Serial P

55ATtiny11/121006C–09/01Electrical CharacteristicsAbsolute Maximum RatingsOperating Temperature... -55°C to +125°C*NOTI

56ATtiny11/121006C–09/01Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.2. “Min” means the lowest value where th

57ATtiny11/121006C–09/01External Clock Drive WaveformsFigure 33. External ClockNote: R should be in the range 3-100 kΩ, and C should be at least 20 p

58ATtiny11/121006C–09/01ATtiny11 Typical CharacteristicsThe following charts show typical behavior. These figures are not tested during manu-facturing

59ATtiny11/121006C–09/01Figure 35. Active Supply Current vs. VCCFigure 36. Active Supply Current vs. VCC, Device Clocked by Internal Oscillator01234

6ATtiny11/121006C–09/01Note: “1” means unprogrammed, “0” means programmed.The various choices for each clocking option give different start-up times a

60ATtiny11/121006C–09/01Figure 37. Active Supply Current vs. VCC, Device Clocked by External 32kHz CrystalFigure 38. Idle Supply Current vs. Frequen

61ATtiny11/121006C–09/01Figure 39. Idle Supply Current vs. VCCFigure 40. Idle Supply Current vs. VCC, Device Clocked by Internal Oscillator0112232 2

62ATtiny11/121006C–09/01Figure 41. Idle Supply Current vs. VCC, Device Clocked by External 32kHz CrystalFigure 42. Power-down Supply Current vs. VCC

63ATtiny11/121006C–09/01Figure 43. Power-down Supply Current vs. VCCFigure 44. Analog Comparator Current vs. VCC01020304050607080901.5 2 2.5 3 3.5 4

64ATtiny11/121006C–09/01Analog comparator offset voltage is measured as absolute offset.Figure 45. Analog Comparator Offset Voltage vs. Common Mode V

65ATtiny11/121006C–09/01Figure 47. Analog Comparator Input Leakage CurrentFigure 48. Watchdog Oscillator Frequency vs. VCC6050403020100-100 0.5 1.51

66ATtiny11/121006C–09/01Sink and source capabilities of I/O ports are measured on one pin at a time.Figure 49. Pull-up Resistor Current vs. Input Vol

67ATtiny11/121006C–09/01Figure 51. I/O Pin Sink Current vs. Output VoltageFigure 52. I/O Pin Source Current vs. Output Voltage010203040506070800 0.5

68ATtiny11/121006C–09/01Figure 53. I/O Pin Sink Current vs. Output VoltageFigure 54. I/O Pin Source Current vs. Output Voltage0510152025300 0.5 1 1.

69ATtiny11/121006C–09/01Figure 55. I/O Pin Input Threshold Voltage vs. VCCFigure 56. I/O Pin Input Hysteresis vs. VCC00.511.522.52.7 4.0 5.0Threshol

7ATtiny11/121006C–09/01External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 5 canbe used. For det

70ATtiny11/121006C–09/01ATtiny12 Typical CharacteristicsThe following charts show typical behavior. These data are characterized, but nottested. All c

71ATtiny11/121006C–09/01Figure 58. Active Supply Current vs. VCC, Device Clocked by External 32kHz CrystalFigure 59. Idle Supply Current vs. VCC, De

72ATtiny11/121006C–09/01Figure 60. Idle Supply Current vs. VCC, Device Clocked by External 32kHz CrystalAnalog Comparator offset voltage is measured

73ATtiny11/121006C–09/01Figure 62. Analog Comparator Offset Voltage vs. Common Mode VoltageFigure 63. Analog Comparator Input Leakage Current0246810

74ATtiny11/121006C–09/01Figure 64. Calibrated RC Oscillator Frequency vs. VCC Figure 65. Watchdog Oscillator Frequency vs. VCCCALIBRATED RC OSCILLAT

75ATtiny11/121006C–09/01Sink and source capabilities of I/O ports are measured on one pin at a time.Figure 66. Pull-up Resistor Current vs. Input Vol

76ATtiny11/121006C–09/01Figure 68. I/O Pin Sink Current vs. Output Voltage (VCC = 5V)Figure 69. I/O Pin Source Current vs. Output Voltage (VCC = 5V)

77ATtiny11/121006C–09/01Figure 70. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V)Figure 71. I/O Pin Source Current vs. Output Voltage (VCC = 2

78ATtiny11/121006C–09/01Figure 72. I/O Pin Input Threshold Voltage vs. VCC (TA = 25°C)Figure 73. I/O Pin Input Hysteresis vs. VCC (TA = 25°C)00.511.

79ATtiny11/121006C–09/01Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addr

8ATtiny11/121006C–09/01Architectural OverviewThe fast-access register file concept contains 32 x 8-bit general-purpose working regis-ters with a singl

80ATtiny11/121006C–09/01Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addre

81ATtiny11/121006C–09/01Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add t

82ATtiny11/121006C–09/01DATA TRANSFER INSTRUCTIONSLD Rd,Z Load Register Indirect Rd ← (Z) None 2ST Z,Rr Store Register Indirect (Z) ← Rr None 2MOV Rd,

83ATtiny11/121006C–09/01Note: The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The internal RC osc

84ATtiny11/121006C–09/01Packaging Information8P310.16(0.400)9.017(0.355)PIN17.11(0.280)6.10(0.240).300 (7.62) REF5.33(0.210) MAX254(0.100) BSC 0.381(0

85ATtiny11/121006C–09/018S2.020 (.508).012 (.305).213 (5.41).205 (5.21).330 (8.38).300 (7.62)PIN 1 .050 (1.27) BSC.212 (5.38).203 (5.16).080 (2.03).07

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

9ATtiny11/121006C–09/01Figure 6. The ATtiny11/12 AVR RISC ArchitectureA flexible interrupt module has its control registers in the I/O space with an