
159
8127B–AVR–08/09
ATtiny4/5/9/10
23. Datasheet Revision History
23.1 Rev. 8127B – 08/09
1. Updated document template
2. Expanded document to also cover devices ATtiny4, ATtiny5 and ATtiny9
3. Added section:
– “Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10” on page 4
4. Updated sections:
– “ADC Clock – clkADC” on page 18
– “Starting from Idle / ADC Noise Reduction / Standby Mode” on page 20
– “ADC Noise Reduction Mode” on page 24
– “Analog to Digital Converter” on page 25
– “SMCR – Sleep Mode Control Register” on page 25
– “PRR – Power Reduction Register” on page 26
– “Alternate Functions of Port B” on page 48
– “Overview” on page 83
– “Physical Layer of Tiny Programming Interface” on page 96
– “Overview” on page 107
– “ADC Characteristics (ATtiny5/10, only) – Preliminary Data” on page 120
– “Supply Current of I/O Modules” on page 122
– “Register Summary” on page 149
– “Ordering Information” on page 153
5. Added figure:
– “Using an External Programmer for In-System Programming via TPI” on page 97
6. Updated figure:
– “Data Memory Map (Byte Addressing)” on page 15
7. Added table:
– “Number of Words and Pages in the Flash (ATtiny4/5)” on page 109
8. Updated tables:
– “Active Clock Domains and Wake-up Sources in Different Sleep Modes” on page 23
– “Reset and Interrupt Vectors” on page 35
– “Number of Words and Pages in the Flash (ATtiny9/10)” on page 109
– “Signature codes” on page 110
23.2 Rev. 8127A – 04/09
1. Initial revision
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