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8127B–AVR–08/09
14.5 Instruction Set
The TPI has a compact instruction set that is used to access the TPI Control and Status Space
(CSS) and the data space. The instructions allow the external programmer to access the TPI,
the NVM Controller and the NVM memories. All instructions except SKEY require one byte oper-
and following the instruction. The SKEY instruction is followed by 8 data bytes. All instructions
are byte-sized.
The TPI instruction set is summarised in Table 14-1.
14.5.1 SLD - Serial LoaD from data space using indirect addressing
The SLD instruction uses indirect addressing to load data from the data space to the TPI physi-
cal layer shift-register for serial read-out. The data space location is pointed by the Pointer
Register (PR), where the address must have been stored before data is accessed. The Pointer
Register is either left unchanged by the operation, or post-incremented, as shown in Table 14-2.
Table 14-1. Instruction Set Summary
Mnemonic Operand Description Operation
SLD data, PR
Serial LoaD from data space using indirect
addressing
data ← DS[PR]
SLD data, PR+
Serial LoaD from data space using indirect
addressing and post-increment
data ← DS[PR]
PR ← PR+1
SST PR, data
Serial STore to data space using indirect
addressing
DS[PR]
← data
SST PR+, data
Serial STore to data space using indirect
addressing and post-increment
DS[PR] ← data
PR ← PR+1
SSTPR PR, a
Serial STore to Pointer Register using direct
addressing
PR[a] ← data
SIN data, a Serial IN from data space data ← I/O[a]
SOUT a, data Serial OUT to data space I/O[a]
← data
SLDCS data, a
Serial LoaD from Control and Status space
using direct addressing
data ← CSS[a]
SSTCS a, data
Serial STore to Control and Status space
using direct addressing
CSS[a]
← data
SKEY Key, {8{data}} Serial KEY Key ← {8{data}}
Table 14-2. The Serial Load from Data Space (SLD) Instruction
Operation Opcode Remarks Register
data ← DS[PR]
0010 0000
PR ← PR
Unchanged
data
← DS[PR]
0010 0100
PR ← PR + 1
Post increment
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