Rainbow-electronics ATmega128RFA1 Manual de usuario Pagina 389
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8266A-MCU Wireless-12/09
ATmega128RFA1
TWCR
TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE
Value
1 X 0 0 X 1 0 X
This scheme is repeated until the last byte has been sent and the transfer is ended by
generating a STOP condition or a repeated START condition. A STOP condition is
generated by writing the following value to TWCR:
TWCR
TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE
Value
1 X 0 1 X 1 0 X
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR
TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE
Value
X 1 0 X 1 0 X
After a REPEATED START condition (state 0x10) the 2-wire Serial Interface can
access the same Slave again, or a new Slave without transmitting a STOP condition.
Repeated START enables the Master to switch between Slaves, Master Transmitter
mode and Master Receiver mode without losing control of the bus.
Figure 25-12. Formats and States in the Master Transmitter Mode
S SLA W A DATA A P
$08
$18 $28
R SLA W
$10
A P
$20
P
$30
A or A
$38
A
Other master
continues
A or A
$38
Other master
continues
R
A
$68
Other master
continues
$78 $B0
To corresponding
states in slave mode
MT
MR
Successfull
transmission
to a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Not acknowledge
received after a data
byte
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
DATA A
n
From master to slave
From slave to master
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero
S
- Features 1
- Applications 1
- 1 Pin Configurations 2
- 2 Disclaimer 2
- • over 10 years at 85°C 8
- • TBD years at 25°C 8
- ATmega128RFA1 11
- 8 AVR Memories 18
- 8.3 EEPROM Data Memory 20
- 8.7 Other Port Registers 26
- Section 34
- 9.4 Operating Modes 35
- is reduced 40
- E v e n t 41
- B lo c k 41
- T R X R S T 41
- XO S C = O N 44
- X O S C =O FF 44
- 51 20 704 56
- 9.5 Functional Description 61
- Frame Length Value Payload 62
- 0 - 4 Reserved 62
- 5 MPDU (Acknowledgement) 62
- 6 – 8 Reserved 62
- 9 - aMaxPHYPacketSize MPDU 62
- )()( xxMxN ⋅= 66
- PHY_ED_LEVEL Description 69
- 0xFF Reset value 69
- Extended Operating Mode 69
- 9.6 Module Description 74
- The receiver is designed to 75
- IC internal 82
- 9.7 Radio Transceiver Usage 83
- ATm ega128R FA 1 89
- 9.10 Abbreviations 98
- 9.11 Reference Documents 100
- 9.12 Register Description 100
- NA ($13D) AES_ER 101
- AES_STATE7:0 AES_STATE 102
- AES_KEY7:0 AES_KEY 102
- 8266A-MCU Wireless-12/09 103
- SFD_VALUE7:0 SFD_VALUE 111
- 2 Antenna 0: DIG1=L, DIG2=H 114
- Antenna Diversity 114
- Bit 7 6 5 4 117
- Read/Write RW RW RW RW 117
- Initial Value 1 1 1 1 117
- RX_PDT_DIS Res2 RX_SYN 118
- Res1 Res0 RX_SYN 118
- Initial Value 0 1 0 1 120
- PART_NUM7:0 PART_NUM 122
- VERSION_NUM7:0 VERSION_NUM 122
- MAN_ID_07:00 MAN_ID_0 123
- MAN_ID_17:10 MAN_ID_1 123
- PAN_ID_07:00 PAN_ID_0 124
- PAN_ID_17:10 PAN_ID_1 124
- IEEE_ADDR_07:00 IEEE_ADDR_0 124
- IEEE_ADDR_17:10 IEEE_ADDR_1 125
- IEEE_ADDR_27:20 IEEE_ADDR_2 125
- IEEE_ADDR_37:30 IEEE_ADDR_3 125
- IEEE_ADDR_47:40 IEEE_ADDR_4 126
- IEEE_ADDR_57:50 IEEE_ADDR_5 126
- IEEE_ADDR_67:60 IEEE_ADDR_6 126
- IEEE_ADDR_77:70 IEEE_ADDR_7 126
- CSMA_SEED_07:00 CSMA_SEED_0 128
- Resx7 Resx6 TST_CTRL_DIGI 131
- Resx5 Resx4 TST_CTRL_DIGI 131
- TRXFBST7:0 TRXFBST 132
- TRXFBEND7:0 TRXFBEND 132
- 10 MAC Symbol Counter 133
- 10.9 Backoff Slot Counter 135
- 10.10 Symbol Counter Usage 135
- 10.11 Register Description 137
- SCCNTHL7:0 SCCNTHL 138
- SCCNTLH7:0 SCCNTLH 138
- SCCNTLL7:0 SCCNTLL 138
- SCTSRHH7:0 SCTSRHH 138
- SCTSRHL7:0 SCTSRHL 139
- SCTSRLH7:0 SCTSRLH 139
- SCTSRLL7:0 SCTSRLL 139
- SCBTSRHH7:0 SCBTSRHH 139
- SCBTSRHL7:0 SCBTSRHL 140
- SCBTSRLH7:0 SCBTSRLH 140
- SCBTSRLL7:0 SCBTSRLL 140
- SCOCR1HH7:0 SCOCR1HH 140
- SCOCR1HL7:0 SCOCR1HL 141
- SCOCR1LH7:0 SCOCR1LH 141
- SCOCR1LL7:0 SCOCR1LL 141
- SCOCR2HH7:0 SCOCR2HH 141
- SCOCR2HL7:0 SCOCR2HL 142
- SCOCR2LH7:0 SCOCR2LH 142
- SCOCR2LL7:0 SCOCR2LL 142
- SCOCR3HH7:0 SCOCR3HH 142
- 11.1 Overview 147
- 11.3 Clock Sources 148
- 11.6 External Clock 150
- 11.8 Clock Output Buffer 152
- 11.10 System Clock Prescaler 152
- 11.11 Register Description 153
- NA ($61) CLKPCE 154
- 12.1 Deep-Sleep Mode 156
- 12.6 Register Description 166
- NA ($12F) Res1 Res0 LLDONE 172
- NA ($136) PFDRV1 174
- 13 System Control and Reset 176
- 13.4 Watchdog Timer 180
- 13.5 Register Description 183
- 14 I/O-Ports 186
- DPDS0/DPDS1 187
- PUOE 0 0 0 0 194
- Alternate Function 198
- 14.4 Register Description 204
- PINB7:0 PINB 206
- PORTD7:0 PORTD 206
- PIND7:0 PIND 207
- PORTE7:0 PORTE 207
- PINE7:0 PINE 208
- PORTF7:0 PORTF 208
- 15 Interrupts 211
- 15.4 Register Description 216
- 16 External Interrupts 218
- 16.2 Register Description 219
- DATA BUS 226
- 17.4 Counter Unit 227
- = (8-bit Comparator ) 229
- 17.7 Modes of Operation 232
- (Toggle) 233
- OC0xPCPWM 236
- 17.9 Register Description 238
- 18.1 Features 244
- 18.2 Overview 244
- 18.5 Counter Unit 249
- 18.6 Input Capture Unit 250
- DATA BUS (8-bit) 251
- 18.7 Output Compare Units 252
- = (16-bit Comparator ) 253
- DATA BUS (8-bit) 253
- 18.9 Modes of Operation 256
- OCnxPCPWM 262
- OCnxPFCPWM 264
- 18.11 Register Description 266
- TCNT1H7:0 TCNT1H 270
- TCNT1L7:0 TCNT1L 271
- OCR1AH7:0 OCR1AH 271
- OCR1AL7:0 OCR1AL 271
- OCR1BH7:0 OCR1BH 272
- OCR1BL7:0 OCR1BL 272
- OCR1CH7:0 OCR1CH 273
- OCR1CL7:0 OCR1CL 273
- ICR1H7:0 ICR1H 273
- ICR1L7:0 ICR1L 274
- NA ($90) COM3A1 276
- TCNT3H7:0 TCNT3H 280
- TCNT3L7:0 TCNT3L 280
- OCR3AH7:0 OCR3AH 281
- OCR3AL7:0 OCR3AL 281
- OCR3BH7:0 OCR3BH 282
- OCR3BL7:0 OCR3BL 282
- OCR3CH7:0 OCR3CH 282
- OCR3CL7:0 OCR3CL 283
- ICR3H7:0 ICR3H 283
- ICR3L7:0 ICR3L 283
- NA ($A0) COM4A1 285
- TCNT4H7:0 TCNT4H 289
- TCNT4L7:0 TCNT4L 289
- OCR4AH7:0 OCR4AH 290
- OCR4AL7:0 OCR4AL 290
- OCR4BH7:0 OCR4BH 291
- OCR4BL7:0 OCR4BL 291
- OCR4CH7:0 OCR4CH 291
- OCR4CL7:0 OCR4CL 292
- ICR4H7:0 ICR4H 292
- ICR4L7:0 ICR4L 292
- NA ($120) COM5A1 294
- TCNT5H7:0 TCNT5H 298
- TCNT5L7:0 TCNT5L 298
- OCR5AH7:0 OCR5AH 299
- OCR5AL7:0 OCR5AL 299
- OCR5BH7:0 OCR5BH 299
- OCR5BL7:0 OCR5BL 300
- OCR5CH7:0 OCR5CH 300
- OCR5CL7:0 OCR5CL 301
- ICR5H7:0 ICR5H 301
- ICR5L7:0 ICR5L 301
- 19.1 Internal Clock Source 304
- 19.2 Prescaler Reset 304
- 19.3 External Clock Source 304
- 19.4 Register Description 305
- 20.1 Overview 307
- 20.2 Description 307
- 20.3 Timing Example 308
- 21.1 Features 309
- 21.2 Overview 309
- 21.4 Counter Unit 311
- 21.5 Modes of Operation 311
- 21.6 Output Compare Unit 316
- 22.1 Features 330
- Functional Description 330
- Pin Functionality 334
- 22.4 Register Description 336
- SPDR7:0 SPDR 338
- 23.3 Clock Generation 340
- 23.5 USART Initialization 344
- 23.10 Register Description 356
- NA ($C2) UMSEL01 358
- UBRR9 UBRR8 UBRR1H 364
- 24 USART in SPI Mode 368
- 24.4 Frame Formats 370
- NA ($CA) UDORD1 376
- Data Stable Data Stable 378
- Data Change 378
- TWI Unit 382
- 25.6 Using the TWI 384
- 1 X 0 0 X 1 0 X 388
- 400
- 26.2 Register Description 408
- 27.1 Features 410
- 27.3 ADC Start-Up 412
- Tracking Phase Duration t 416
- Settling Time t 418
- 097.0)2000/( ⋅+Ω= 420
- Output Code 422
- NA ($7B) AVDDOK 428
- 28.3 TAP - Test Access Port 436
- 28.9 Bibliography 440
- MSB LSB 442
- 29.5 Boundary-scan Chain 444
- See Boundary-scan 446
- Description for Details! 446
- 30.1 Features 450
- 30.7 Register Description 462
- 31 Memory Programming 464
- 31.3 Signature Bytes 466
- LOAD ADDRESS 476
- (LOW BYTE) 476
- Bit 15 B 0 480
- Program Memory/ 480
- EEPROM Memory 480
- Programming Enable 484
- 33 Register Summary 496
- 34.2 Clock Characteristics 502
- Figure 34-2 504
- Single Ended Conversion 506
- Single Ended Conversion 506
- Gain = 200x 506
- 35 Typical Characteristics 510
- 37 Packaging Information 512
- 39 Revision history 516
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