Rainbow-electronics ATmega128RFA1 Manual de usuario descargar pdf (Pagina 374)

374

8266A-MCU Wireless-12/09

ATmega128RFA1

• Bit 5 – UDRE0 - USART Data Register Empty

The UDRE0 Flag indicates if the transmit buffer (UDR0) is ready to receive new data. If

UDRE0 is one, the buffer is empty, and therefore ready to be written. The UDRE0 Flag

can generate a Data Register Empty interrupt (see description of the UDRIE0 bit).

UDRE0 is set after a reset to indicate that the Transmitter is ready.

24.6.4 UCSR0B – USART0 MSPIM Control and Status Register B

Bit 7 6 5 4 3 2 1 0

NA ($C1) RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSR0B

Read/Write RW RW RW RW RW

Initial Value 0 0 1 0 0

• Bit 7 – RXCIE0 - RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXC0 Flag. A USART Receive Complete

interrupt will be generated only if the RXCIE0 bit is written to one, the Global Interrupt

Flag in SREG is written to one and the RXC0 bit in UCSR0A is set.

• Bit 6 – TXCIE0 - TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXC0 Flag. A USART Transmit Complete

interrupt will be generated only if the TXCIE0 bit is written to one, the Global Interrupt

Flag in SREG is written to one and the TXC0 bit in UCSR0A is set.

• Bit 5 – UDRIE0 - USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDRE0 Flag. A Data Register Empty

interrupt will be generated only if the UDRIE0 bit is written to one, the Global Interrupt

Flag in SREG is written to one and the UDRE0 bit in UCSR0A is set.

• Bit 4 – RXEN0 - Receiver Enable

Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will

override normal port operation for the RxD0 pin when enabled. Disabling the Receiver

will flush the receive buffer. Only enabling the receiver in MSPI mode (i.e. setting

RXEN0=1 and TXEN0=0) has no meaning since it is the transmitter that controls the

transfer clock and since only master mode is supported.

• Bit 3 – TXEN0 - Transmitter Enable

Writing this bit to one enables the USART Transmitter. The Transmitter will override

normal port operation for the TxD0 pin when enabled. The disabling of the Transmitter

(writing TXEN0 to zero) will not become effective until ongoing and pending

transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer

longer override the TxD0 port.

24.6.5 UCSR0C – USART0 MSPIM Control and Status Register C

Bit 7 6 5 4 3 2 1 0

NA ($C2) UDORD0

UCPHA0

UCPOL0

UCSR0C

Read/Write RW RW RW

Initial Value 1 1 0

• Bit 2 – UDORD0 - Data Order

1 2 ... 369 370 371 372 373 374 375 376 377 378 379 ... 523 524

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