
W90P710CD/W90P710CDG
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6.3.2.3 SDRAM Interface
MCLK
MCKE
nSCS[1:0]
nSRAS
nSCAS
nSWE
nSDQM[3:0]
A[21:0]
D[31:0]
A[10:0]
DQ[[31:0]
DQM[3:0]
nWE
nCAS
nRAS
nCS
BS0
BS1
CLK
CKE
W90P710
A13
A14
A[10:0]
nSCS0
SDRAM
64Mb 512Kx4x32
nSDQM[3:0]
Fig 6.3.1 SDRAM Interface
6.3.3 EBI Control Registers Map
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
EBICON
0xFFF0_1000
R/W EBI control register
0x0001_0000
ROMCON
0xFFF0_1004
R/W ROM/FLASH control register
0x0000_0XFC
SDCONF0 0xFFF0_1008 R/W SDRAM bank 0 configuration register
0x0000_0800
SDCONF1 0xFFF0_100C R/W SDRAM bank 1 configuration register
0x0000_0800
SDTIME0 0xFFF0_1010 R/W SDRAM bank 0 timing control register
0x0000_0000
SDTIME1
0xFFF0_1014
R/W SDRAM bank 1 timing control register
0x0000_0000
EXT0CON
0xFFF0_1018
R/W External I/O 0 control register
0x0000_0000
EXT1CON
0xFFF0_101C
R/W External I/O 1 control register
0x0000_0000
EXT2CON
0xFFF0_1020
R/W External I/O 2 control register
0x0000_0000
EXT3CON
0xFFF0_1024
R/W External I/O 3 control register
0x0000_0000
CKSKEW
0xFFF0_1F00
R/W Clock skew control register (for testing)
0xXXXX_0038
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