Rainbow-electronics W90P710CDG Manual de usuario descargar pdf (Pagina 178)

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BITS DESCRIPTION

[1] WDH

WritebackDoneHead

Set after the Host Controller has written HcDoneHead to

HccaDoneHead.

[0] SCHO

SchedulingOverrun

Set when the List Processor determines a Schedule Overrun has

occurred.

Host Controller Interrupt Enable Register

Writing a ‘1’ to a bit in this register sets the corresponding bit, while writing a ‘0’ leaves the bit

unchanged.

RESET

VALUE

HcInterruptEnable 0xFFF0_5010

R/W Host Controller Interrupt Enable Register 0x0000_0000

31 30 29 28 27 26 25 24

MIE OCE Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1 0

Reserved RHCE FNOE UREE RDTE SOFE WDHE SCHOE

BITS DESCRIPTION

[31] MIE

MasterInterruptEnable

This bit is a global interrupt enable. A write of ‘1’ allows interrupts to

be enabled via the specific enable bits listed above.

[30] OCE

OwnershipChangeEnable

0: Ignore

1: Enable interrupt generation due to Ownership Change.

[29:7] Reserved

Reserved. Read/Write 0's

[6] RHSCE

RootHubStatusChangeEnable

0: Ignore

1: Enable interrupt generation due to Root Hub Status Change.

1 2 ... 173 174 175 176 177 178 179 180 181 182 183 ... 551 552

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Rainbow-electronics W90P710CDG Manual de usuario Pagina 178

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